Add LM3S6965 definition

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2654 7fd9a85b-ad96-42d3-883c-3090e2eb8679

6 files changed, 367 insertions, 56 deletions

diff --git a/nuttx/arch/arm/include/lm3s/irq.h b/nuttx/arch/arm/include/lm3s/irq.h
index e10a884d50..37629a37ba 100644
--- a/nuttx/arch/arm/include/lm3s/irq.h
+++ b/nuttx/arch/arm/include/lm3s/irq.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/include/lm3s/irq.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -75,7 +75,7 @@
 /* External interrupts (vectors >= 16) */
 
 #define LM3S_IRQ_INTERRUPTS  (16) /* Vector number of the first external interrupt */
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
 
 #  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
 #  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
@@ -115,11 +115,55 @@
 #  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
 #  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
                                   /* Vectors 60-70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM3S_IRQ_GPIOA     (16) /* Vector 16: GPIO Port A */
+#  define LM3S_IRQ_GPIOB     (17) /* Vector 17: GPIO Port B */
+#  define LM3S_IRQ_GPIOC     (18) /* Vector 18: GPIO Port C */
+#  define LM3S_IRQ_GPIOD     (19) /* Vector 19: GPIO Port D */
+#  define LM3S_IRQ_GPIOE     (20) /* Vector 20: GPIO Port E */
+#  define LM3S_IRQ_UART0     (21) /* Vector 21: UART 0 */
+#  define LM3S_IRQ_UART1     (22) /* Vector 22: UART 1 */
+#  define LM3S_IRQ_SSI0      (23) /* Vector 23: SSI 0 */
+#  define LM3S_IRQ_I2C0      (24) /* Vector 24: I2C 0 */
+#  define LM3S_IRQ_PWMFAULT  (25) /* Vector 25: PWM Fault */
+#  define LM3S_IRQ_PWM0      (26) /* Vector 26: PWM Generator 0 */
+#  define LM3S_IRQ_PWM1      (27) /* Vector 27: PWM Generator 1 */
+#  define LM3S_IRQ_PWM2      (28) /* Vector 28: PWM Generator 2 */
+#  define LM3S_IRQ_QEI0      (29) /* Vector 29: QEI0 */
+#  define LM3S_IRQ_ADC0      (30) /* Vector 30: ADC Sequence 0 */
+#  define LM3S_IRQ_ADC1      (31) /* Vector 31: ADC Sequence 1 */
+#  define LM3S_IRQ_ADC2      (32) /* Vector 32: ADC Sequence 2 */
+#  define LM3S_IRQ_ADC3      (33) /* Vector 33: ADC Sequence 3 */
+#  define LM3S_IRQ_WDOG      (34) /* Vector 34: Watchdog Timer */
+#  define LM3S_IRQ_TIMER0A   (35) /* Vector 35: Timer 0 A */
+#  define LM3S_IRQ_TIMER0B   (36) /* Vector 36: Timer 0 B */
+#  define LM3S_IRQ_TIMER1A   (37) /* Vector 37: Timer 1 A */
+#  define LM3S_IRQ_TIMER1B   (38) /* Vector 38: Timer 1 B */
+#  define LM3S_IRQ_TIMER2A   (39) /* Vector 39: Timer 2 A */
+#  define LM3S_IRQ_TIMER2B   (40) /* Vector 40: Timer 3 B */
+#  define LM3S_IRQ_COMPARE0  (41) /* Vector 41: Analog Comparator 0 */
+#  define LM3S_IRQ_COMPARE1  (42) /* Vector 42: Analog Comparator 1 */
+                                  /* Vector 43: Reserved */
+#  define LM3S_IRQ_SYSCON    (44) /* Vector 44: System Control */
+#  define LM3S_IRQ_FLASHCON  (45) /* Vector 45: FLASH Control */
+#  define LM3S_IRQ_GPIOF     (46) /* Vector 46: GPIO Port F */
+#  define LM3S_IRQ_GPIOG     (47) /* Vector 47: GPIO Port G */
+                                  /* Vector 48: Reserved */
+#  define LM3S_IRQ_UART2     (49) /* Vector 49: UART 2 */
+                                  /* Vector 50: Reserved */
+#  define LM3S_IRQ_TIMER3A   (51) /* Vector 51: Timer 3 A */
+#  define LM3S_IRQ_TIMER3B   (52) /* Vector 52: Timer 3 B */
+#  define LM3S_IRQ_I2C1      (53) /* Vector 53: I2C 1 */
+#  define LM3S_IRQ_QEI1      (54) /* Vector 54: QEI1 */
+                                  /* Vectors 55-57: Reserved */
+#  define LM3S_IRQ_ETHCON    (58) /* Vector 58: Ethernet Controller */
+#  define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
+                                  /* Vectors 60-70: Reserved */
 #else
 #  error "IRQ Numbers not specified for this LM3S chip"
 #endif
 
-#define NR_IRQS              (60) /* Really only 43 */
+#define NR_IRQS              (60) /* (Really less because of reserved vectors) */
 
 /* GPIO IRQs -- Note that support for individual GPIO ports can
  * be disabled in order to reduce the size of the implemenation.
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index d96b6fb0fb..d95861247f 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lm3s/chip.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,13 +48,28 @@
 
 /* Get customizations for each supported chip (only the LM3S6918 right now) */
 
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LM3S_NSSI            2  /* Two SSI modules */
 #  define LM3S_NUARTS          2  /* Two UART modules */
 #  define LM3S_NI2C            2  /* Two I2C modules */
-#  define LM3S_NSSI            2  /* Two SSI modules */
-#  define LM3S_NETHCONTROLLERS 1  /* One ethenet controller */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            0  /* No PWM modules */
+#  define LM3S_NQEI            0  /* No quadrature encoders */
+#  define LC3S_NGPIOS          38 /* 5-38 GPIOs, depending on configuration */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+#  define LM3S_NTIMERS         4  /* Four general purpose timers */
+#  define LM3S_NETHCONTROLLERS 1  /* One Ethernet controller */
+#  define LM3S_NSSI            1  /* One SSI module */
+#  define LM3S_NUARTS          3  /* Three UART modules */
+#  define LM3S_NI2C            2  /* Two I2C modules */
+#  define LM3S_NADC            1  /* One ADC module */
+#  define LM2S_NPWM            3  /* Three PWM modules */
+#  define LM3S_NQEI            2  /* Two quadrature encoders */
+#  define LC3S_NGPIOS          42 /* 0-42 GPIOs */
 #else
-#  error "No Ethernet support for this LM3S chip"
+#  error "Capabilities not specified for this LM3S chip"
 #endif
 
 /* Then get all of the register definitions */
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h
index 2548e6c5b7..dd51e7a9bd 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_internal.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lm3s/lm3s_internal.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -153,43 +153,99 @@
  * hardware function for each pin.
  */
 
-#define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)    /* PA0: UART 0 receive (U0Rx) */
-#define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1)   /* PA1: UART 0 transmit (U0Tx) */
-#define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)       /* PA2: SSI0 clock (SSI0Clk) */
-#define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)       /* PA3: SSI0 frame (SSI0Fss) */
-#define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)    /* PA4: SSI0 receive (SSI0Rx) */
-#define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5)   /* PA5: SSI0 transmit (SSI0Tx) */
-#define GPIO_PWM1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)       /* PA6: Capture/Compare/PWM1 (CCP1) */
-#define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)     /* PA7: I2C1 data (I2C1SDA) */
-#define GPIO_PWM0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)       /* PB0: Capture/Compare/PWM0 (CCP0) */
-#define GPIO_PWM2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)       /* PB1: Capture/Compare/PWM2 (CCP2) */
-#define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2)   /* PB2: I2C0 clock (I2C0SCL) */
-#define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)     /* PB3: I2C0 data (I2C0SDA) */
-#define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)    /* PB4: Analog comparator 0 negative input (C0-) */
-#define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)    /* PB5: Analog comparator 1 negative input (C1-) */
-#define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)    /* PB6: Analog comparator 0 positive input (C0+) */
-#define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)    /* PB7: JTAG ~TRST */
-#define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)    /* PC0: JTAG/SWD CLK */
-#define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)    /* PC0: JTAG/SWD CLK */
-#define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)       /* PC1: JTAG TMS */
-#define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)       /* PC1: JTAG SWDIO */
-#define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)    /* PC2: JTAG TDI */
-#define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3)   /* PC3: JTAG TDO */
-#define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3)   /* PC3: JTAG SWO */
-#define GPIO_PWM5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)       /* PC4: Capture/Compare/PWM5 (CCP5) */
-#define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)    /* PC5: Analog comparator 1 positive input (C1+) */
-#define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5)   /* PC5: Analog comparator 0 output (C0o) */
-#define GPIO_PWM3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)       /* PC6: Capture/Compare/PWM3 (CCP3) */
-#define GPIO_PWM4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)       /* PC7: Capture/Compare/PWM4 (CCP4) */
-#define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)    /* PD2: UART 1 receive (U1Rx) */
-#define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3)   /* PD3: UART 1 transmit (U1Tx) */
-#define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)       /* PE0: SSI1 clock (SSI1Clk) */
-#define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)       /* PE1: SSI1 frame (SSI1Fss) */
-#define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)    /* PE2: SSI1 receive (SSI1Rx) */
-#define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3)   /* PE3: SSI1 transmit (SSI1Tx) */
-#define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2)   /* PF2: LED1 */
-#define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3)   /* PF3: LED0 */
-#define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0)   /* PG0: I2C1 clock (I2C1SCL) */
+#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTA | 6)     /* PA6: Capture/Compare/PWM1 (CCP1) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 0)     /* PB0: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTB | 1)     /* PB1: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_TMR5_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 4)     /* PC4: Capture/Compare/PWM5 (CCP5) */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_TMR4_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 7)     /* PC7: Capture/Compare/PWM4 (CCP4) */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
+#ifdef CONFIG_ARCH_CHIP_LM3S6965
+#  define GPIO_UART0_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0)  /* PA0: UART 0 receive (U0Rx) */
+#  define GPIO_UART0_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
+#  define GPIO_SSI0_CLK    (GPIO_FUNC_PFIO | GPIO_PORTA | 2)     /* PA2: SSI0 clock (SSI0Clk) */
+#  define GPIO_SSI0_FSS    (GPIO_FUNC_PFIO | GPIO_PORTA | 3)     /* PA3: SSI0 frame (SSI0Fss) */
+#  define GPIO_SSI0_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4)  /* PA4: SSI0 receive (SSI0Rx) */
+#  define GPIO_SSI0_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
+#  define GPIO_I2C1_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */
+#  define GPIO_I2C1_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTA | 7)   /* PA7: I2C1 data (I2C1SDA) */
+#  define GPIO_PWM1_2      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
+#  define GPIO_PWM1_3      (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
+#  define GPIO_I2C0_SCL    (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
+#  define GPIO_I2C0_SDA    (GPIO_FUNC_PFODIO | GPIO_PORTB | 3)   /* PB3: I2C0 data (I2C0SDA) */
+#  define GPIO_CMP0_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4)  /* PB4: Analog comparator 0 negative input (C0-) */
+#  define GPIO_CMP1_NIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5)  /* PB5: Analog comparator 1 negative input (C1-) */
+#  define GPIO_CMP0_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6)  /* PB6: Analog comparator 0 positive input (C0+) */
+#  define GPIO_JTAG_TRST   (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7)  /* PB7: JTAG ~TRST */
+#  define GPIO_JTAG_TCK    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_SWCLK  (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0)  /* PC0: JTAG/SWD CLK */
+#  define GPIO_JTAG_TMS    (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG TMS */
+#  define GPIO_JTAG_SWDIO  (GPIO_FUNC_PFIO | GPIO_PORTC | 1)     /* PC1: JTAG SWDIO */
+#  define GPIO_JTAG_TDI    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2)  /* PC2: JTAG TDI */
+#  define GPIO_JTAG_TDO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
+#  define GPIO_JTAG_SWO    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
+#  define GPIO_QEI0_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4)  /* PC4: QEI module 0 phase A. */
+#  define GPIO_CMP1_PIN    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5)  /* PC5: Analog comparator 1 positive input (C1+) */
+#  define GPIO_CMP0_OUT    (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
+#  define GPIO_TMR3_CCP    (GPIO_FUNC_PFIO | GPIO_PORTC | 6)     /* PC6: Capture/Compare/PWM3 (CCP3) */
+#  define GPIO_QEI0_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7)  /* PC7: QEI module 0 phase B. */
+#  define GPIO_QEI0_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1)  /* PD0: QEI module 0 index. ) */
+#  define GPIO_PWM0_1      (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */
+#  define GPIO_UART1_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2)  /* PD2: UART 1 receive (U1Rx) */
+#  define GPIO_UART1_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
+#  define GPIO_TMR0_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 4)     /* PC4: Capture/Compare/PWM0 (CCP0) */
+#  define GPIO_TMR2_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 5)     /* PC5: Capture/Compare/PWM2 (CCP2) */
+#  define GPIO_PWM_FAULT   (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6)  /* PC5: PWM Fault */
+#  define GPIO_TMR1_CCP    (GPIO_FUNC_PFIO | GPIO_PORTD | 7)     /* PC5: Capture/Compare/TMR1 (CCP1) */
+#  define GPIO_SSI1_CLK    (GPIO_FUNC_PFIO | GPIO_PORTE | 0)     /* PE0: SSI1 clock (SSI1Clk) */
+#  define GPIO_SSI1_FSS    (GPIO_FUNC_PFIO | GPIO_PORTE | 1)     /* PE1: SSI1 frame (SSI1Fss) */
+#  define GPIO_SSI1_RX     (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: SSI1 receive (SSI1Rx) */
+#  define GPIO_SSI1_TX     (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
+#  define GPIO_PWM2_4      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
+#  define GPIO_PWM2_5      (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
+#  define GPIO_QEI1_PHB    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2)  /* PE2: QEI module 1 phase B. */
+#  define GPIO_QEI1_PHA    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3)  /* PE3: QEI module 1 phase A. */
+#  define GPIO_PWM0_0      (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */
+#  define GPIO_QEI1_IDX    (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1)  /* PD0: QEI module 1 index. ) */
+#  define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
+#  define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
+#  define GPIO_UART2_RX    (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0)  /* PA0: UART 0 receive (UGRx) */
+#  define GPIO_UART2_TX    (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
+#else
+#  error "Unknown LM3S chip"
+#endif
+
 
 /************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
index 70d37b0c02..81e312cf14 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
@@ -1,7 +1,7 @@
 /**************************************************************************
  * arch/arm/src/lm3s/lm3s_lowputc.c
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -54,17 +54,37 @@
 
 /* Configuration **********************************************************/
 
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_UART1_DISABLE
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#  define CONFIG_UART1_DISABLE 1
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_UART2_DISABLE
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#  define CONFIG_UART2_DISABLE 1
+#endif
+
 /* Is there a serial console? */
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE) && !defined(CONFIG_UART0_DISABLE)
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
 #  define HAVE_CONSOLE 1
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && !defined(CONFIG_UART1_DISABLE)
 #  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && !defined(CONFIG_UART2_DISABLE)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
 #  define HAVE_CONSOLE 1
 #else
+#  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
 #  undef CONFIG_UART0_SERIAL_CONSOLE
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
 #  undef HAVE_CONSOLE
 #endif
 
@@ -82,6 +102,12 @@
 #  define LM3S_CONSOLE_BITS     CONFIG_UART1_BITS
 #  define LM3S_CONSOLE_PARITY   CONFIG_UART1_PARITY
 #  define LM3S_CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define LM3S_CONSOLE_BASE     LM3S_UART2_BASE
+#  define LM3S_CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define LM3S_CONSOLE_BITS     CONFIG_UART2_BITS
+#  define LM3S_CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define LM3S_CONSOLE_2STOP    CONFIG_UART2_2STOP
 #else
 #  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
 #endif
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
index c3ffab27df..5179e3550e 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lm3s/lm3s_memorymap.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,7 +48,7 @@
 
 /* Memory map ***********************************************************************/
  
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6965)
 #  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
                                          /* -0x1fffffff: Reserved */
 #  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
@@ -72,8 +72,13 @@
 #endif
 
 /* Peripheral base addresses ********************************************************/
+/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
+ * peripheral modules.  They could probably be combined into one peripheral memory
+ * map.  However, keeping them separate does also provide so early, compile-time
+ * error detection that makes the duplication worthwhile.
+ */
 
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
 /* FiRM Peripheral Base Addresses */
 
 #  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
@@ -115,6 +120,53 @@
 #  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                             /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#else
 #else
 #  error "Peripheral base addresses not specified for this LM3S chip"
 #endif
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_serial.c b/nuttx/arch/arm/src/lm3s/lm3s_serial.c
index f8cde80e7a..2d693bd42c 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_serial.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_serial.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/lm3s/lm3s_serial.c
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -64,6 +64,18 @@
 
 /* Some sanity checks *******************************************************/
 
+#if LM3S_NUARTS < 2
+#  undef  CONFIG_UART1_DISABLE
+#  undef  CONFIG_UART1_SERIAL_CONSOLE
+#  define CONFIG_UART1_DISABLE 1
+#endif
+
+#if LM3S_NUARTS < 3
+#  undef  CONFIG_UART2_DISABLE
+#  undef  CONFIG_UART2_SERIAL_CONSOLE
+#  define CONFIG_UART2_DISABLE 1
+#endif
+
 /* Is there a UART enabled? */
 
 #if defined(CONFIG_UART0_DISABLE) && defined(CONFIG_UART1_DISABLE)
@@ -74,14 +86,21 @@
 
 #if defined(CONFIG_UART0_SERIAL_CONSOLE) && !defined(CONFIG_UART0_DISABLE)
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
 #  define HAVE_CONSOLE 1
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && !defined(CONFIG_UART1_DISABLE)
 #  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && !defined(CONFIG_UART2_DISABLE)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
 #  define HAVE_CONSOLE 1
 #else
 #  warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting"
 #  undef CONFIG_UART0_SERIAL_CONSOLE
 #  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
 #  undef HAVE_CONSOLE
 #endif
 
@@ -98,34 +117,93 @@
 #  define TTYS0_DEV       g_uart0port     /* UART0 is ttyS0 */
 #  ifndef CONFIG_UART1_DISABLE
 #    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
 #  else
-#    undef TTYS1_DEV                      /* No ttyS1 */
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
 #  endif
 #elif defined(CONFIG_UART1_SERIAL_CONSOLE)
 #  define CONSOLE_DEV     g_uart1port     /* UART1 is console */
 #  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
 #  ifndef CONFIG_UART0_DISABLE
 #    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
 #  else
-#    undef TTYS1_DEV                      /* No ttyS1 */
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
+#  endif
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_uart2port     /* UART2 is console */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
+#  ifndef CONFIG_UART0_DISABLE
+#    define TTYS1_DEV     g_uart0port     /* UART0 is ttyS1 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
+#  else
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
 #  endif
 #elif !defined(CONFIG_UART0_DISABLE)
 #  undef  CONSOLE_DEV                     /* No console device */
 #  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
 #  ifndef CONFIG_UART1_DISABLE
 #    define TTYS1_DEV     g_uart1port     /* UART1 is ttyS1 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS2_DEV   g_uart2port     /* UART2 is ttyS2 */
+#    else
+#      undef TTYS2_DEV                    /* No ttyS2 */
+#    endif
 #  else
-#    undef TTYS1_DEV                      /* No ttyS1 */
+#    undef TTYS2_DEV                      /* No ttyS2 */
+#    ifndef CONFIG_UART2_DISABLE
+#      define TTYS1_DEV   g_uart2port     /* UART2 is ttyS1 */
+#    else
+#      undef TTYS1_DEV                    /* No ttyS1 */
+#    endif
 #  endif
 #elif !defined(CONFIG_UART1_DISABLE)
 #  undef  CONSOLE_DEV                     /* No console device */
 #  define TTYS0_DEV       g_uart1port     /* UART1 is ttyS0 */
+#  undef TTYS2_DEV                        /* No ttyS2 */
+#  ifndef CONFIG_UART2_DISABLE
+#    define TTYS1_DEV     g_uart2port     /* UART2 is ttyS1 */
+#  else
+#    undef TTYS1_DEV                      /* No ttyS1 */
+#  endif
+#elif !defined(CONFIG_UART2_DISABLE)
+#  undef  CONSOLE_DEV                     /* No console device */
+#  define TTYS0_DEV       g_uart2port     /* UART2 is ttyS0 */
 #  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
 #else
 #  error "No valid TTY devices"
 #  undef  CONSOLE_DEV                     /* No console device */
 #  undef  TTYS0_DEV                       /* No ttyS0 */
 #  undef  TTYS1_DEV                       /* No ttyS1 */
+#  undef  TTYS2_DEV                       /* No ttyS2 */
 #endif
 
 /****************************************************************************
@@ -191,8 +269,12 @@ static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
 static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
 static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
 #endif
+#ifndef CONFIG_UART2_DISABLE
+static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
+#endif
 
-/* This describes the state of the LM3S6918 uart0 port. */
+/* This describes the state of the LM3S uart0 port. */
 
 #ifndef CONFIG_UART0_DISABLE
 static struct up_dev_s g_uart0priv =
@@ -222,7 +304,7 @@ static uart_dev_t g_uart0port =
 };
 #endif
 
-/* This describes the state of the LM3S6918 uart1 port. */
+/* This describes the state of the LM3S uart1 port. */
 
 #ifndef CONFIG_UART1_DISABLE
 static struct up_dev_s g_uart1priv =
@@ -252,6 +334,36 @@ static uart_dev_t g_uart1port =
 };
 #endif
 
+/* This describes the state of the LM3S uart1 port. */
+
+#ifndef CONFIG_UART2_DISABLE
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase       = LM3S_UART2_BASE,
+  .baud           = CONFIG_UART2_BAUD,
+  .irq            = LM3S_IRQ_UART2,
+  .parity         = CONFIG_UART2_PARITY,
+  .bits           = CONFIG_UART2_BITS,
+  .stopbits2      = CONFIG_UART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART2_RXBUFSIZE,
+    .buffer = g_uart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART2_TXBUFSIZE,
+    .buffer = g_uart2txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart2priv,
+};
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -850,6 +962,9 @@ void up_earlyserialinit(void)
 #ifdef TTYS1_DEV
   up_disableuartint(TTYS1_DEV.priv, NULL);
 #endif
+#ifdef TTYS2_DEV
+  up_disableuartint(TTYS2_DEV.priv, NULL);
+#endif
 
   /* Configuration whichever one is the console */
 
@@ -882,6 +997,9 @@ void up_serialinit(void)
 #ifdef TTYS1_DEV
   (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
 #endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
 }
 
 /****************************************************************************