Add clock initialization logic for the Nucleus2g boad

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2741 7fd9a85b-ad96-42d3-883c-3090e2eb8679

7 files changed, 286 insertions, 4 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/Make.defs b/nuttx/arch/arm/src/lpc17xx/Make.defs
index 1817c9ef20..5b5c04f612 100755
--- a/nuttx/arch/arm/src/lpc17xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc17xx/Make.defs
@@ -51,8 +51,9 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 # Required LPC17xx files
 
 CHIP_ASRCS	=
-CHIP_CSRCS	= lpc17_allocateheap.c lpc17_gpio.c lpc17_gpioint.c lpc17_irq.c \
-		  lpc17_lowputc.c lpc17_serial.c lpc17_start.c lpc17_timerisr.c
+CHIP_CSRCS	= lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpio.c \
+		  lpc17_gpioint.c lpc17_irq.c lpc17_lowputc.c lpc17_serial.c \
+		  lpc17_start.c lpc17_timerisr.c
 
 # Configuration-dependent LPC17xx files
 
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c
new file mode 100755
index 0000000000..83a3e7a670
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c
@@ -0,0 +1,206 @@
+/****************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_clockconfig.c
+ * arch/arm/src/chip/lpc17_clockconfig.c
+ *
+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "lpc17_internal.h"
+#include "lpc17_syscon.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/************************************************************************************
+ * Name: lpc17_clockconfig
+ *
+ * Description:
+ *   Called to initialize the LPC17xx.  This does whatever setup is needed to put the
+ *   SoC in a usable state.  This includes the initialization of clocking using the
+ *   settings in board.h.
+ *
+ ************************************************************************************/
+
+void lpc17_clockconfig(void)
+{
+  /* Enable the main oscillator (or not) and the frequency range of the main oscillator */
+
+  putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
+
+  /* Wait for the main oscillator to be ready. */
+
+#ifdef CONFIG_LPC17_MAINOSC
+  while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
+#endif
+
+  /* Setup up the divider value for the CPU clock.  The output of the divider is CCLK.
+   * The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK
+   * will be further divided to produce peripheral clocks, but that peripheral clock
+   * setup is performed in the peripheral device drivers.  Here only CCLK is
+   * configured.
+   */
+
+  putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG);
+
+  /* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
+
+#if CONFIG_LPC17_PLL0
+  /* Select the PLL0 source clock, multiplier, and pre-divider values.  NOTE that
+   * a special "feed" sequence must be written to the PLL0FEED register in order
+   * for changes to the PLL0CFG register to take effect.
+   */
+
+  putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
+  putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
+  putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL0FEED);
+
+  /* Enable the PLL. NOTE that a special "feed" sequence must be written to the
+   * PLL0FEED register in order for changes to the PLL0CON register to take effect.
+   */
+
+  putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
+  putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL0FEED);
+
+  /* Wait for PLL0 to lock */
+
+  while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
+
+  /* Enable and connect PLL0 */
+
+  putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
+  putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL0FEED);
+
+  /* Wait for PLL to report that it is connected and enabled */
+
+  while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) == 0);
+#endif
+
+  /* PLL1 receives its clock input from the main oscillator only and can be used to
+   * provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
+   * obtained from PLL0).
+   */
+
+#ifdef CONFIG_LPC17_PLL1
+  /* Select the PLL1 multiplier, and pre-divider values.  NOTE that a special "feed"
+   * sequence must be written to the PLL1FEED register in order for changes to the
+   * PLL1CFG register to take effect.
+   */
+
+  putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
+  putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL1FEED);
+
+  /* Enable the PLL. NOTE that a special "feed" sequence must be written to the
+   * PLL1FEED register in order for changes to the PLL1CON register to take effect.
+   */
+
+  putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
+  putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL1FEED);
+
+  /* Wait for PLL1 to lock */
+
+  while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
+
+  /* Enable and connect PLL1 */
+
+  putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
+  putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
+  putreg32(0x55, LPC17_SYSCON_PLL1FEED);
+
+  /* Wait for PLL to report that it is connected and enabled */
+
+  while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) == 0);
+#else
+  /* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
+
+  putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
+#endif
+
+  /* Disable all peripheral clocks.  They must be configured by each device driver
+   * when the device driver is initialized.
+   */
+
+  putreg32(0, LPC17_SYSCON_PCLKSEL0);
+  putreg32(0, LPC17_SYSCON_PCLKSEL1);
+
+  /* Disable power to all peripherals.  They must be re-powered one at a time by each
+   * device driver when the driver is initialized.
+   */
+
+  putreg32(0, LPC17_SYSCON_PCONP);
+
+  /* Disable CLKOUT */
+
+  putreg32(0, LPC17_SYSCON_CLKOUTCFG);
+
+  /* Configure FLASH */
+
+#ifdef CONFIG_LP17_FLASH
+  putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
+#endif
+}
+
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
index 13b0c48fd8..12294b5b9f 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_syscon.h
@@ -213,8 +213,8 @@
 #define SYSCON_CLKSRCSEL_SHIFT        (0)         /* Bits 0-1: Clock selection */

 #define SYSCON_CLKSRCSEL_MASK         (3 << SYSCON_CLKSRCSEL_SHIFT)

 #  define SYSCON_CLKSRCSEL_INTRC      (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */

-#  define SYSCON_CLKSRCSEL_RTC        (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */

-#  define SYSCON_CLKSRCSEL_MAIN       (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */

+#  define SYSCON_CLKSRCSEL_MAIN       (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */

+#  define SYSCON_CLKSRCSEL_RTC        (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */

                                                   /* Bits 2-31:  Reserved */

 

 /* Clocking and power control - Phase locked loops */

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c
index 07ab46463a..aa113463a9 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_timerisr.c
@@ -42,6 +42,7 @@
 #include <stdint.h>
 #include <time.h>
 #include <debug.h>
+
 #include <nuttx/arch.h>
 #include <arch/board/board.h>
 
diff --git a/nuttx/configs/nucleus2g/README.txt b/nuttx/configs/nucleus2g/README.txt
index 2b9b16d19b..d2cfd733c3 100755
--- a/nuttx/configs/nucleus2g/README.txt
+++ b/nuttx/configs/nucleus2g/README.txt
@@ -286,6 +286,9 @@ Nucleus 2G Configuration Options
 	   the delay actually is 100 seconds.

 

 	Individual subsystems can be enabled:

+	  CONFIG_LPC17_MAINOSC=y

+	  CONFIG_LPC17_PLL0=y

+	  CONFIG_LPC17_PLL1=n

 	  CONFIG_LPC17_ETHERNET=n

 	  CONFIG_LPC17_USBHOST=n

 	  CONFIG_LPC17_USBOTG=n

@@ -315,6 +318,7 @@ Nucleus 2G Configuration Options
 	  CONFIG_LPC17_ADC=n

 	  CONFIG_LPC17_DAC=n

 	  CONFIG_LPC17_GPDMA=n

+	  CONFIG_LP17_FLASH=n

 

   LPC17xx specific device driver settings

 

diff --git a/nuttx/configs/nucleus2g/include/board.h b/nuttx/configs/nucleus2g/include/board.h
index b10b7c4bd0..edbc1bacc1 100755
--- a/nuttx/configs/nucleus2g/include/board.h
+++ b/nuttx/configs/nucleus2g/include/board.h
@@ -48,9 +48,78 @@
  ************************************************************************************/
 
 /* Clocking *************************************************************************/
+/* NOTE:  The following definitions require lpc17_syscon.h.  It is not included here
+ * because the including C file may not have that file in its include path.
+ */
+
+#define BOARD_XTAL_FREQUENCY        (12000000)            /* XTAL oscillator frequency */
+#define BOARD_OSCCLK_FREQUENCY      BOARD_XTAL_FREQUENCY  /* Main oscillator frequency */
+#define BOARD_RTCCLK_FREQUENCY      (32000)               /* RTC oscillator frequency */
+#define BOARD_INTRCOSC_FREQUENCY    (4000000)             /* Internal RC oscillator frequency */
+
+/* This is the clock setup we configure for:
+ *
+ *   SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz  -> Select Main oscillator for source
+ *   PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
+ *   CCLCK = 480MHz / 6 = 80MHz               -> CCLK divider = 6
+ */
 
 #define LPC17_CCLK                 80000000 /* 80Mhz*/
 
+/* Select the main oscillator as the frequency source.  SYSCLK is then the frequency
+ * of the main osciallator.
+ */
+
+#undef CONFIG_LPC17_MAINOSC
+#define CONFIG_LPC17_MAINOSC 1
+#define BOARD_SCS_VALUE            SYSCON_SCS_OSCEN
+
+/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
+ * The input to the divider (PLLCLK) will be determined by the PLL output.
+ */
+
+#define BOARD_CCLKCFG_DIVIDER      6
+#define BOARD_CCLKCFG_VALUE        ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
+
+/* PLL0.  PLL0 is used to generate the CPU clock divider input (PLLCLK).
+ *
+ *  Source clock:               Main oscillator
+ *  PLL0 Multiplier value (M):  20 
+ *  PLL0 Pre-divider value (N): 1
+ */
+
+#undef CONFIG_LPC17_PLL0
+#define CONFIG_LPC17_PLL0 1
+#define BOARD_CLKSRCSEL_VALUE      SYSCON_CLKSRCSEL_MAIN
+
+#define BOARD_PLL0CFG_MSEL         20
+#define BOARD_PLL0CFG_NSEL         1
+#define BOARD_PLL0CFG_VALUE \
+  (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
+   ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
+
+/* PLL1 -- Not used. */
+
+#undef CONFIG_LPC17_PLL0
+#define BOARD_PLL1CFG_MSEL         36
+#define BOARD_PLL1CFG_NSEL         1
+#define BOARD_PLL1CFG_VALUE \
+  (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
+   ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
+
+/* USB divider.  This divder is used when PLL1 is not enabled to get the USB clock
+ * from PLL0:
+ *
+ *  USBCLK = PLL0CLK / 10 = 48MHz
+ */
+
+#define BOARD_USBCLKCFG_VALUE      SYSCON_USBCLKCFG_DIV10
+
+/* FLASH Configuration */
+
+#undef  CONFIG_LP17_FLASH
+#define CONFIG_LP17_FLASH          1
+#define BOARD_FLASHCFG_VALUE       0x0000303a
 
 /* LED definitions ******************************************************************/
 
diff --git a/nuttx/configs/nucleus2g/ostest/defconfig b/nuttx/configs/nucleus2g/ostest/defconfig
index 0dbab33a69..26b9035cd2 100755
--- a/nuttx/configs/nucleus2g/ostest/defconfig
+++ b/nuttx/configs/nucleus2g/ostest/defconfig
@@ -101,6 +101,7 @@ CONFIG_LPC17_BUILDROOT=y
 #  Individual subsystems can be enabled:
 #
 # Individual subsystems can be enabled:
+# (MAINOSC, PLL0, PLL1 and FLASH are controlled in board.h)
 CONFIG_LPC17_ETHERNET=n
 CONFIG_LPC17_USBHOST=n
 CONFIG_LPC17_USBOTG=n