Add MIPS32 interrupt controls

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@3620 7fd9a85b-ad96-42d3-883c-3090e2eb8679

5 files changed, 242 insertions, 26 deletions

diff --git a/nuttx/arch/mips/src/mips32/mips32-cp0.h b/nuttx/arch/mips/include/mips32/cp0.h
index 1cf844b886..3e3b2f7ddd 100755
--- a/nuttx/arch/mips/src/mips32/mips32-cp0.h
+++ b/nuttx/arch/mips/include/mips32/cp0.h
@@ -1,5 +1,5 @@
 /********************************************************************************************

- * arch/mips/src/mips32/mips32-cp0.h

+ * arch/mips/include/mips32/cp0.h

  *

  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.

  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

@@ -33,8 +33,8 @@
  *

  ********************************************************************************************/

 

-#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H

-#define __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H

+#ifndef __ARCH_MIPS_INCLUDE_MIPS32_CP0_H

+#define __ARCH_MIPS_INCLUDE_MIPS32_CP0_H

 

 /********************************************************************************************

  * Included Files

@@ -178,15 +178,18 @@
 #define CP0_STATUS_KX               (1 << 7)  /* Bit 7: Enables 64-bit kernel address space (Not MIPS32) */

 #define CP0_STATUS_IM_SHIFT         (8)       /* Bits 8-15: Interrupt Mask */

 #define CP0_STATUS_IM_MASK          (0xff << CP0_STATUS_IM_SHIFT)

+#  define CP0_STATUS_IM_SWINTS      (0x03 << CP0_STATUS_IM_SHIFT) /* IM0-1 = Software interrupts */

 #  define CP0_STATUS_IM0            (0x01 << CP0_STATUS_IM_SHIFT)

 #  define CP0_STATUS_IM1            (0x02 << CP0_STATUS_IM_SHIFT)

+#  define CP0_STATUS_IM_HWINTS      (0x7c << CP0_STATUS_IM_SHIFT) /* IM2-6 = Hardware interrupts */

 #  define CP0_STATUS_IM2            (0x04 << CP0_STATUS_IM_SHIFT)

 #  define CP0_STATUS_IM3            (0x08 << CP0_STATUS_IM_SHIFT)

 #  define CP0_STATUS_IM4            (0x10 << CP0_STATUS_IM_SHIFT)

 #  define CP0_STATUS_IM5            (0x20 << CP0_STATUS_IM_SHIFT)

 #  define CP0_STATUS_IM6            (0x40 << CP0_STATUS_IM_SHIFT)

+#  define CP0_STATUS_IM_TIMER       (0x80 << CP0_STATUS_IM_SHIFT) /* IM7 = Hardware/Timer/Perf interrupts */

 #  define CP0_STATUS_IM7            (0x80 << CP0_STATUS_IM_SHIFT)

-#define CP0_STATUS_IMPL_SHIFT       (16)      /* Bits 16-17: Interrupt Mask */

+#define CP0_STATUS_IMPL_SHIFT       (16)      /* Bits 16-17: Implementation dependent */

 #define CP0_STATUS_IMPL_MASK        (3 << CP0_STATUS_IMPL_SHIFT)

 #define CP0_STATUS_NMI              (1 << 19) /* Bit 19: Reset exception due to an NMI */

 #define CP0_STATUS_SR               (1 << 20) /* Bit 20: Reset exception due to a Soft Reset */

@@ -532,4 +535,4 @@ extern "C" {
 #endif

 

 #endif /* __ASSEMBLY__ */

-#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H */

+#endif /* __ARCH_MIPS_INCLUDE_MIPS32_CP0_H */

diff --git a/nuttx/arch/mips/include/mips32/irq.h b/nuttx/arch/mips/include/mips32/irq.h
index 845eddaad7..1dea3c7951 100755
--- a/nuttx/arch/mips/include/mips32/irq.h
+++ b/nuttx/arch/mips/include/mips32/irq.h
@@ -44,6 +44,8 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/types.h>
+
 /****************************************************************************
  * Definitions
  ****************************************************************************/
@@ -92,6 +94,39 @@ extern "C" {
 #define EXTERN extern
 #endif
 
+/****************************************************************************
+ * Name: irqsave
+ *
+ * Description:
+ *   Save the current interrupt state and disable interrupts.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Interrupt state prior to disabling interrupts.
+ *
+ ****************************************************************************/
+
+EXTERN irqstate_t irqsave(void);
+
+/****************************************************************************
+ * Name: irqrestore
+ *
+ * Description:
+ *   Restore the previous interrupt state (i.e., the one previously returned
+ *   by irqsave())
+ *
+ * Input Parameters:
+ *   state - The interrupt state to be restored.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+EXTERN void irqrestore(irqstate_t irqtate);
+
 #undef EXTERN
 #ifdef __cplusplus
 }
diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-cp0.h b/nuttx/arch/mips/include/pic32mx/cp0.h
index 2ad658d3a1..6ad9e6d82d 100755
--- a/nuttx/arch/mips/src/pic32mx/pic32mx-cp0.h
+++ b/nuttx/arch/mips/include/pic32mx/cp0.h
@@ -1,5 +1,5 @@
 /****************************************************************************

- * arch/mips/src/pic32mx/pic32mx-cp0.h

+ * arch/mips/include/pic32mx/cp0.h

  *

  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.

  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>

@@ -33,8 +33,8 @@
  *

  ****************************************************************************/

 

-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H

-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H

+#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H

+#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H

 

 /****************************************************************************

  * Included Files

@@ -42,7 +42,7 @@
 

 #include <nuttx/config.h>

 

-#include "mips32-cp0.h"

+#include <arch/mips32/cp0.h>

 

 /****************************************************************************

  * Pre-Processor Definitions

@@ -71,13 +71,13 @@
  *   exception

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *

  * Register Number: 9 Sel: 0 Name: Count

  * Function: Processor cycle count

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *

  * Register Number: 10 Reserved.

  * Compliance Level: Required for TLB-based MMU; Optional otherwise.

@@ -86,20 +86,20 @@
  * Function: Timer interrupt control

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  */

 

 /* Register Number: 12 Sel: 0 Name: Status

  * Function: Processor status and control

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *   NOTES:

  *   1. The following are reserved bits in the PIC32: 

  *      CP0_STATUS_UX   Bit 5: Enables 64-bit user address space (Not MIPS32)

  *      CP0_STATUS_SX   Bit 6: Enables 64-bit supervisor address space (Not MIPS32)

  *      CP0_STATUS_KX   Bit 7: Enables 64-bit kernel address space (Not MIPS32)

- *      CP0_STATUS_IMPL Bits 16-17: Interrupt Mask

+ *      CP0_STATUS_IMPL Bits 16-17: Implementation dependent

  *      CP0_STATUS_TS   Bit 21: TLB detected match on multiple entries

  *      CP0_STATUS_PX   Bit 23: Enables 64-bit operations (Not MIPS32)

  *      CP0_STATUS_MX   Bit 24: Enables MDMX™ (Not MIPS32)

@@ -196,7 +196,7 @@
  * Function: Cause of last general exception

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *   NOTES: The following bits are added in the PIC32: 

  */

  

@@ -208,14 +208,14 @@
  * Function: Program counter at last exception

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  */

 

 /* Register Number: 15 Sel: 0 Name: PRId

  * Function: Processor identification and revision

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *   NOTE: Slightly different bit interpretations of some fields:

  */

 

@@ -240,7 +240,7 @@
  * Function: Configuration register

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *   1. PIC32MX is always little-endian.

  *   2. Implementation specific bits defined.

  */

@@ -265,13 +265,13 @@
  * Function: Configuration register 1

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *

  * Register Number: 16 Sel: 2 Name: Config2

  * Function: Configuration register 2

  * Compliance Level: Optional.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  */

 

 #undef CP0_CONFIG2_TBS_SHIFT

@@ -281,7 +281,7 @@
  * Function: Configuration register 3

  * Compliance Level: Optional.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  */

 

 #define CP0_CONFIG3_SP              (1 << 4)  /* Bit 4: Support page bit */

@@ -332,7 +332,7 @@
  * Function: Program counter at last EJTAG debug exception

  * Compliance Level: Optional.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *

  * Register Number: 25-29 Reserved

  * Compliance Level: Recommended/Optional.

@@ -341,13 +341,13 @@
  * Function: Program counter at last error

  * Compliance Level: Required.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  *

  * Register Number: 31 Sel: 0 Name: DeSAVE

  * Function: EJTAG debug exception save register

  * Compliance Level: Optional.

  *

- *   See arch/mips/src/mips32/mips32-cp0.h

+ *   See arch/mips/include/mips32/cp0.h

  */

 

 /****************************************************************************

@@ -377,4 +377,4 @@ extern "C" {
 #endif

 

 #endif /* __ASSEMBLY__ */

-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H */

+#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */

diff --git a/nuttx/arch/mips/src/mips32/up_irq.c b/nuttx/arch/mips/src/mips32/up_irq.c
new file mode 100644
index 0000000000..3ca1359ce8
--- /dev/null
+++ b/nuttx/arch/mips/src/mips32/up_irq.c
@@ -0,0 +1,178 @@
+/****************************************************************************
+ * arch/mips/src/mips32/up_irq.c
+ *
+ *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+#include <arch/types.h>
+#include <arch/mips32/cp0.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cp0_getstatus
+ *
+ * Description:
+ *   Disable interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline irqstate_t cp0_getstatus(void)
+{
+  register irqstate_t status;
+  __asm__ __volatile__
+    (
+      "\t.set    push\n"
+      "\t.set    noat\n"
+      "\t mfc0   %0,$12\n"         /* Get CP0 status register */
+      "\t.set    pop\n"
+      : "=r" (status)
+      :
+      : "memory"
+    );
+
+  return status;
+}
+
+/****************************************************************************
+ * Name: cp0_putstatus
+ *
+ * Description:
+ *   Disable interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void cp0_putstatus(irqstate_t status)
+{
+  __asm__ __volatile__
+    (
+      "\t.set    push\n"
+      "\t.set    noat\n"
+      "\t.set    noreorder\n"
+      "\tmtc0   %0,$12\n"          /* Set the status to the provided value */
+      "\tnop\n"                    /* MTC0 status hazard: */
+      "\tnop\n"                    /* Recommended spacing: 3 */
+      "\tnop\n"
+      "\tnop\n"                    /* Plus one for good measure */
+      "\t.set    pop\n"
+      : 
+      : "r" (status)
+      : "memory"
+    );
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: irqsave
+ *
+ * Description:
+ *   Save the current interrupt state and disable interrupts.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Interrupt state prior to disabling interrupts.
+ *
+ ****************************************************************************/
+
+irqstate_t irqsave(void)
+{
+  register irqstate_t status;
+  register irqstate_t ret;
+
+  status  = cp0_getstatus();       /* Get CP0 status */
+  ret     = status;                /* Save the status */
+  status &= ~CP0_STATUS_IM_MASK;   /* Clear all interrupt mask bits */
+  status |= CP0_STATUS_IM_SWINTS;  /* Keep S/W interrupts enabled */
+  cp0_putstatus(status);           /* Disable interrupts */
+  return ret;                      /* Return status before interrtupts disabled */
+}
+
+/****************************************************************************
+ * Name: irqrestore
+ *
+ * Description:
+ *   Restore the previous interrutp state (i.e., the one previously returned
+ *   by irqsave())
+ *
+ * Input Parameters:
+ *   state - The interrupt state to be restored.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void irqrestore(irqstate_t irqstate)
+{
+  register irqstate_t status;
+
+  status    = cp0_getstatus();      /* Get CP0 status */
+  status   &= ~CP0_STATUS_IM_MASK;  /* Clear all interrupt mask bits */
+  irqstate &= CP0_STATUS_IM_MASK;   /* Retain interrupt mask bits only */
+  status   |= irqstate;             /* Set new interrupt mask bits */
+  status   |= CP0_STATUS_IM_SWINTS; /* Make sure that S/W interrupts enabled */
+  cp0_putstatus(status);            /* Restore interrupt state */
+}
diff --git a/nuttx/arch/mips/src/pic32mx/Make.defs b/nuttx/arch/mips/src/pic32mx/Make.defs
index be5296f1d7..dee8fa3337 100755
--- a/nuttx/arch/mips/src/pic32mx/Make.defs
+++ b/nuttx/arch/mips/src/pic32mx/Make.defs
@@ -40,7 +40,7 @@ HEAD_ASRC =
 # Common MIPS files
 
 CMN_ASRCS = 
-CMN_CSRCS = up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
+CMN_CSRCS = up_irq.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 
 # Required PIC32MX files