From 7c6773f6fff2e52a249832172eeb3f292d819a4e Mon Sep 17 00:00:00 2001 From: Pau Espin Pedrol Date: Wed, 2 Aug 2023 21:22:22 +0200 Subject: rlcmac: ul_tbf: Factor out function configuring TBF to lower layers This code part will also be used by tbf_ul_ass_fsm.c to temporarily configure lower layers with ctx->phase1_alloc in order to receive RTS indications which the RLC/MAC uses to tick the FSM in state GPRS_RLCMAC_TBF_UL_ASS_ST_WAIT_TBF_STARTING_TIME1. Change-Id: I174327b25b726662a6b5902008e205ddb3de2fe0 --- include/osmocom/gprs/rlcmac/tbf_ul.h | 4 ++++ src/rlcmac/tbf_ul.c | 30 ++++++++++++++++++++++++++++++ src/rlcmac/tbf_ul_fsm.c | 22 ++-------------------- tests/rlcmac/rlcmac_prim_test.err | 32 ++++++++++++++++---------------- 4 files changed, 52 insertions(+), 36 deletions(-) diff --git a/include/osmocom/gprs/rlcmac/tbf_ul.h b/include/osmocom/gprs/rlcmac/tbf_ul.h index fe9db64..1abde9a 100644 --- a/include/osmocom/gprs/rlcmac/tbf_ul.h +++ b/include/osmocom/gprs/rlcmac/tbf_ul.h @@ -52,6 +52,10 @@ struct gprs_rlcmac_ul_tbf { struct gprs_rlcmac_ul_tbf *gprs_rlcmac_ul_tbf_alloc(struct gprs_rlcmac_entity *gre); void gprs_rlcmac_ul_tbf_free(struct gprs_rlcmac_ul_tbf *ul_tbf); +int gprs_rlcmac_ul_tbf_submit_configure_req(const struct gprs_rlcmac_ul_tbf *ul_tbf, + const struct gprs_rlcmac_ul_tbf_allocation *alloc, + bool starting_time_present, uint32_t starting_time_fn); + void gprs_rlcmac_ul_tbf_countdown_proc_update_cv(struct gprs_rlcmac_ul_tbf *ul_tbf); bool gprs_rlcmac_ul_tbf_in_contention_resolution(const struct gprs_rlcmac_ul_tbf *ul_tbf); diff --git a/src/rlcmac/tbf_ul.c b/src/rlcmac/tbf_ul.c index 369be55..3786b30 100644 --- a/src/rlcmac/tbf_ul.c +++ b/src/rlcmac/tbf_ul.c @@ -102,6 +102,36 @@ void gprs_rlcmac_ul_tbf_free(struct gprs_rlcmac_ul_tbf *ul_tbf) gprs_rlcmac_entity_ul_tbf_freed(gre, ul_tbf); } +int gprs_rlcmac_ul_tbf_submit_configure_req(const struct gprs_rlcmac_ul_tbf *ul_tbf, + const struct gprs_rlcmac_ul_tbf_allocation *alloc, + bool starting_time_present, uint32_t starting_time_fn) +{ + struct osmo_gprs_rlcmac_prim *rlcmac_prim; + + rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_cfg_ul_tbf_req(ul_tbf->tbf.nr, 0x00); + + if (starting_time_present) + rlcmac_prim->l1ctl.cfg_ul_tbf_req.start_fn = starting_time_fn; + + for (unsigned int tn = 0; tn < ARRAY_SIZE(alloc->ts); tn++) { + const struct gprs_rlcmac_ul_tbf_allocation_ts *ts; + + ts = &alloc->ts[tn]; + if (!ts->allocated) + continue; + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask |= (1 << tn); + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_usf[tn] = ts->usf; + } + + LOGPTBFUL(ul_tbf, LOGL_INFO, + "Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=%u ul_slotmask=0x%02x tbf_starting_time(present=%u fn=%u)\n", + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_tbf_nr, + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask, + starting_time_present, starting_time_fn); + + return gprs_rlcmac_prim_call_down_cb(rlcmac_prim); +} + /* whether the UL TBF is in Contention Resolution state (false = already succeeded)*/ bool gprs_rlcmac_ul_tbf_in_contention_resolution(const struct gprs_rlcmac_ul_tbf *ul_tbf) { diff --git a/src/rlcmac/tbf_ul_fsm.c b/src/rlcmac/tbf_ul_fsm.c index 7639d83..3c041a6 100644 --- a/src/rlcmac/tbf_ul_fsm.c +++ b/src/rlcmac/tbf_ul_fsm.c @@ -59,26 +59,8 @@ static const struct osmo_tdef_state_timeout tbf_ul_fsm_timeouts[32] = { static int configure_ul_tbf(const struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx) { - struct osmo_gprs_rlcmac_prim *rlcmac_prim; - - rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_cfg_ul_tbf_req(ctx->tbf->nr, 0x00); - - for (unsigned int tn = 0; tn < ARRAY_SIZE(ctx->ul_tbf->cur_alloc.ts); tn++) { - const struct gprs_rlcmac_ul_tbf_allocation_ts *ts; - - ts = &ctx->ul_tbf->cur_alloc.ts[tn]; - if (!ts->allocated) - continue; - rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask |= (1 << tn); - rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_usf[tn] = ts->usf; - } - - LOGPFSML(ctx->fi, LOGL_INFO, - "Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=%u ul_slotmask=0x%02x\n", - rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_tbf_nr, - rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask); - - return gprs_rlcmac_prim_call_down_cb(rlcmac_prim); + return gprs_rlcmac_ul_tbf_submit_configure_req(ctx->ul_tbf, &ctx->ul_tbf->cur_alloc, + false, 0); } static int release_ul_tbf(const struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx) diff --git a/tests/rlcmac/rlcmac_prim_test.err b/tests/rlcmac/rlcmac_prim_test.err index 913c9da..21bd98e 100644 --- a/tests/rlcmac/rlcmac_prim_test.err +++ b/tests/rlcmac/rlcmac_prim_test.err @@ -17,7 +17,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -92,7 +92,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -116,7 +116,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -140,7 +140,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -164,7 +164,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -197,7 +197,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -235,7 +235,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -270,7 +270,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -305,7 +305,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -353,7 +353,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -499,7 +499,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -527,7 +527,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -595,7 +595,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -709,7 +709,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -819,7 +819,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss TFI=0 initCS=CS-2 startTimeF DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00002342) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -965,7 +965,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_PKT_UL_ASS}: Received Event RX_PKT_UL_ASS DLGLOBAL DEBUG Register POLL (TS=7 FN=43, reason=UL_ASS) DLGLOBAL INFO UL_TBF_ASS{WAIT_PKT_UL_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0xc0 +DLGLOBAL INFO TBF(UL:NR-0:TLLI-00000001) Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0xc0 tbf_starting_time(present=0 fn=0) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE -- cgit v1.2.3