rlcmac: deal with RACH retransmissions (drop rach_req_ra)

The RA value does change during RACH retransmissions, so we cannot
expect a specific value in gprs_rlcmac_handle_ccch_imm_ass_ul_tbf()
anymore.  Offload checking it to the lower layers.

* Rename submit_rach_req() to submit_packet_access_req().
* Get rid of gen_chan_req(), indicate only the access cause.

Ideally, we should also rename the OSMO_GPRS_RLCMAC_L1CTL_RACH
to something like OSMO_GPRS_RLCMAC_L1CTL_PKT_CHAN_ACCESS, but
let's better do this separately.

Change-Id: If0de3ed86b1e2897d70183f3b0f4fbfd7d2bda80
Related: osmocom-bb.git Iab6d9147f6e0aeb99239affacf318a3897fd6ffe
Related: OS#5500, OS#6131

5 files changed, 49 insertions, 54 deletions

diff --git a/include/osmocom/gprs/rlcmac/tbf_ul_ass_fsm.h b/include/osmocom/gprs/rlcmac/tbf_ul_ass_fsm.h
index ad32471..162517d 100644
--- a/include/osmocom/gprs/rlcmac/tbf_ul_ass_fsm.h
+++ b/include/osmocom/gprs/rlcmac/tbf_ul_ass_fsm.h
@@ -35,7 +35,6 @@ struct gprs_rlcmac_tbf_ul_ass_fsm_ctx {
 	};
 	const struct gprs_rlcmac_dl_tbf *dl_tbf; /* Not null if assignment was started by a DL TBF ACK/NACK */
 	enum gprs_rlcmac_tbf_ul_ass_type ass_type;
-	uint8_t rach_req_ra;
 	struct gprs_rlcmac_ul_tbf_allocation phase1_alloc;
 	struct gprs_rlcmac_ul_tbf_allocation phase2_alloc;
 	bool tbf_starting_time_exists;
@@ -85,7 +84,7 @@ int gprs_rlcmac_tbf_ul_ass_start_from_releasing_ul_tbf(struct gprs_rlcmac_ul_tbf
 int gprs_rlcmac_tbf_ul_ass_start_from_dl_tbf_ack_nack(struct gprs_rlcmac_ul_tbf *ul_tbf, const struct gprs_rlcmac_dl_tbf *dl_tbf, uint8_t tn);
 
 bool gprs_rlcmac_tbf_ul_ass_pending(struct gprs_rlcmac_ul_tbf *ul_tbf);
-bool gprs_rlcmac_tbf_ul_ass_match_rach_req(struct gprs_rlcmac_ul_tbf *ul_tbf, uint8_t ra);
+bool gprs_rlcmac_tbf_ul_ass_wait_ccch_imm_ass(const struct gprs_rlcmac_ul_tbf *ul_tbf);
 bool gprs_rlcmac_tbf_ul_ass_waiting_tbf_starting_time(const struct gprs_rlcmac_ul_tbf *ul_tbf);
 void gprs_rlcmac_tbf_ul_ass_fn_tick(const struct gprs_rlcmac_ul_tbf *ul_tbf, uint32_t fn, uint8_t ts_nr);
 bool gprs_rlcmac_tbf_ul_ass_rts(const struct gprs_rlcmac_ul_tbf *ul_tbf, const struct gprs_rlcmac_rts_block_ind *bi);
diff --git a/src/rlcmac/rlcmac.c b/src/rlcmac/rlcmac.c
index 212b801..2c809ec 100644
--- a/src/rlcmac/rlcmac.c
+++ b/src/rlcmac/rlcmac.c
@@ -219,7 +219,7 @@ static int gprs_rlcmac_handle_ccch_imm_ass_ul_tbf(uint8_t ts_nr, uint32_t fn, co
 		ul_tbf = gre->ul_tbf;
 		if (!ul_tbf)
 			continue;
-		if (!gprs_rlcmac_tbf_ul_ass_match_rach_req(ul_tbf, ia->req_ref.ra))
+		if (!gprs_rlcmac_tbf_ul_ass_wait_ccch_imm_ass(ul_tbf))
 			continue;
 		rc = osmo_fsm_inst_dispatch(ul_tbf->ul_ass_fsm.fi,
 					    GPRS_RLCMAC_TBF_UL_ASS_EV_RX_CCCH_IMM_ASS,
diff --git a/src/rlcmac/tbf_ul_ass_fsm.c b/src/rlcmac/tbf_ul_ass_fsm.c
index 5587ddb..64797aa 100644
--- a/src/rlcmac/tbf_ul_ass_fsm.c
+++ b/src/rlcmac/tbf_ul_ass_fsm.c
@@ -103,27 +103,24 @@ free_ret:
 	return NULL;
 }
 
-/* Generate a 8-bit CHANNEL REQUEST message as per 3GPP TS 44.018, 9.1.8 */
-static uint8_t gen_chan_req(bool single_block)
-{
-	uint8_t rnd = (uint8_t)rand();
-
-	if (single_block) /* 01110xxx */
-		return 0x70 | (rnd & 0x07);
-
-	/* 011110xx or 01111x0x or 01111xx0 */
-	if ((rnd & 0x07) == 0x07)
-		return 0x78;
-	return 0x78 | (rnd & 0x07);
-}
-
-static int submit_rach_req(struct gprs_rlcmac_tbf_ul_ass_fsm_ctx *ctx)
+static int submit_packet_access_req(const struct gprs_rlcmac_tbf_ul_ass_fsm_ctx *ctx)
 {
 	struct osmo_gprs_rlcmac_prim *rlcmac_prim;
-	ctx->rach_req_ra = gen_chan_req(ctx->ass_type == GPRS_RLCMAC_TBF_UL_ASS_TYPE_2PHASE);
 
-	LOGPFSML(ctx->fi, LOGL_INFO, "Send RACH.req ra=0x%02x\n", ctx->rach_req_ra);
-	rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_rach8_req(ctx->rach_req_ra);
+	switch (ctx->ass_type) {
+	case GPRS_RLCMAC_TBF_UL_ASS_TYPE_1PHASE:
+		/* 3GPP TS 44.018, table 9.1.8.1: cause 011110xx or 01111x0x or 01111xx0 */
+		LOGPFSML(ctx->fi, LOGL_INFO, "Requesting one-phase packet access using CCCH\n");
+		rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_rach8_req(0x78);
+		break;
+	case GPRS_RLCMAC_TBF_UL_ASS_TYPE_2PHASE:
+		/* 3GPP TS 44.018, table 9.1.8.1: cause 011110xx */
+		LOGPFSML(ctx->fi, LOGL_INFO, "Requesting two-phase packet access using CCCH\n");
+		rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_rach8_req(0x70);
+		break;
+	/* TODO: EGPRS specific modes (11-bit RACH) */
+	}
+
 	return gprs_rlcmac_prim_call_down_cb(rlcmac_prim);
 }
 
@@ -271,7 +268,7 @@ static void st_idle(struct osmo_fsm_inst *fi, uint32_t event, void *data)
 		/* Inform the main TBF state about the assignment starting: */
 		osmo_fsm_inst_dispatch(ctx->ul_tbf->state_fsm.fi, GPRS_RLCMAC_TBF_UL_EV_UL_ASS_START, NULL);
 		ctx->ass_type = *(enum gprs_rlcmac_tbf_ul_ass_type *)data;
-		rc = submit_rach_req(ctx);
+		rc = submit_packet_access_req(ctx);
 		if (rc < 0) {
 			osmo_fsm_inst_dispatch(ctx->ul_tbf->state_fsm.fi, GPRS_RLCMAC_TBF_UL_EV_UL_ASS_REJ, NULL);
 			break;
@@ -702,10 +699,9 @@ bool gprs_rlcmac_tbf_ul_ass_pending(struct gprs_rlcmac_ul_tbf *ul_tbf)
 	return ul_tbf->ul_ass_fsm.fi->state != GPRS_RLCMAC_TBF_UL_ASS_ST_IDLE;
 }
 
-bool gprs_rlcmac_tbf_ul_ass_match_rach_req(struct gprs_rlcmac_ul_tbf *ul_tbf, uint8_t ra)
+bool gprs_rlcmac_tbf_ul_ass_wait_ccch_imm_ass(const struct gprs_rlcmac_ul_tbf *ul_tbf)
 {
-	return ul_tbf->ul_ass_fsm.fi->state == GPRS_RLCMAC_TBF_UL_ASS_ST_WAIT_CCCH_IMM_ASS &&
-		ul_tbf->ul_ass_fsm.rach_req_ra == ra;
+	return ul_tbf->ul_ass_fsm.fi->state == GPRS_RLCMAC_TBF_UL_ASS_ST_WAIT_CCCH_IMM_ASS;
 }
 
 bool gprs_rlcmac_tbf_ul_ass_waiting_tbf_starting_time(const struct gprs_rlcmac_ul_tbf *ul_tbf)
diff --git a/tests/rlcmac/rlcmac_prim_test.err b/tests/rlcmac/rlcmac_prim_test.err
index 25653e0..c76fe8f 100644
--- a/tests/rlcmac/rlcmac_prim_test.err
+++ b/tests/rlcmac/rlcmac_prim_test.err
@@ -7,7 +7,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7e
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -85,7 +85,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x79
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -109,7 +109,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7b
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -133,7 +133,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x79
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -157,7 +157,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x78
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -190,7 +190,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7a
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -229,7 +229,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7c
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -265,7 +265,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x79
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -301,7 +301,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7d
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -348,7 +348,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7a
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL INFO Rx from upper layers: GRR-UNITDATA.request
@@ -507,7 +507,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_RELEASE.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7b
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_DATA.request
@@ -536,7 +536,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7a
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -606,7 +606,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7b
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -726,7 +726,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7b
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
@@ -843,7 +843,7 @@ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Allocated
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START
 DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START
 DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN
-DLGLOBAL INFO UL_TBF_ASS{IDLE}: Send RACH.req ra=0x7e
+DLGLOBAL INFO UL_TBF_ASS{IDLE}: Requesting one-phase packet access using CCCH
 DLGLOBAL DEBUG Tx to lower layers: L1CTL-RACH.request
 DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to WAIT_CCCH_IMM_ASS
 DLGLOBAL DEBUG Rx from lower layers: L1CTL-CCCH_DATA.indication
diff --git a/tests/rlcmac/rlcmac_prim_test.ok b/tests/rlcmac/rlcmac_prim_test.ok
index 0c66e24..dcaa816 100644
--- a/tests/rlcmac/rlcmac_prim_test.ok
+++ b/tests/rlcmac/rlcmac_prim_test.ok
@@ -1,6 +1,6 @@
 === test_ul_tbf_attach start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7e
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
@@ -14,21 +14,21 @@ sys={0.027690}, mono={0.027690}: Expect defer_pkt_idle_timer timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
 === test_ul_tbf_t3164_timeout start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 sys={5.000000}, mono={5.000000}: clock_override_add
 sys={5.000000}, mono={5.000000}: Expect T3164 timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 sys={10.000000}, mono={10.000000}: clock_override_add
 sys={10.000000}, mono={10.000000}: Expect T3164 timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 sys={15.000000}, mono={15.000000}: clock_override_add
@@ -47,7 +47,7 @@ sys={20.027690}, mono={20.027690}: Expect defer_pkt_idle_timer timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
 === test_ul_tbf_t3166_timeout start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
@@ -56,7 +56,7 @@ sys={5.000000}, mono={5.000000}: clock_override_add
 sys={5.000000}, mono={5.000000}: Expect T3166 timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7c
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ]
@@ -64,7 +64,7 @@ sys={10.000000}, mono={10.000000}: clock_override_add
 sys={10.000000}, mono={10.000000}: Expect T3166 timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ]
@@ -72,7 +72,7 @@ sys={15.000000}, mono={15.000000}: clock_override_add
 sys={15.000000}, mono={15.000000}: Expect T3166 timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7d
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ]
@@ -85,7 +85,7 @@ sys={20.027690}, mono={20.027690}: Expect defer_pkt_idle_timer timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
 === test_ul_tbf_n3104_timeout start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 RTS 0: FN=8
@@ -115,7 +115,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=52 ts=7 data_len=34 da
 RTS 11: FN=56
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=56 ts=7 data_len=34 data=[00 01 04 3d 00 00 23 42 71 62 f2 24 6c 84 44 04 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
@@ -123,7 +123,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 === test_ul_tbf_t3182_timeout start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
@@ -138,7 +138,7 @@ sys={5.027690}, mono={5.027690}: Expect defer_pkt_idle_timer timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
 === test_ul_tbf_last_data_cv0_retrans_max start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
@@ -159,7 +159,7 @@ sys={0.027690}, mono={0.027690}: Expect defer_pkt_idle_timer timeout
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request
 === test_ul_tbf_countdown_procedure start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
@@ -180,7 +180,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=30 ts=7 data_len=34 da
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
 === test_ul_tbf_request_another_ul_tbf start ===
 sys={0.000000}, mono={0.000000}: clock_override_set
-test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7e
+test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78
 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request
 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80
 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342