python/trx: fork RadioInterfaceUHD from RadioInterface

Change-Id: I1644a3f6b8da0d5f2a1a133058269e5383948fda

1 files changed, 66 insertions, 0 deletions

diff --git a/python/trx/radio_if_uhd.py b/python/trx/radio_if_uhd.py
new file mode 100644
index 0000000..0b2ef7a
--- /dev/null
+++ b/python/trx/radio_if_uhd.py
@@ -0,0 +1,66 @@
+#!/usr/bin/env python2
+# -*- coding: utf-8 -*-
+
+# GR-GSM based transceiver
+# Radio interface for UHD devices
+#
+# (C) 2019 by Vadim Yanitskiy <axilirator@gmail.com>
+#
+# All Rights Reserved
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+from gnuradio import uhd
+
+from radio_if import RadioInterface
+
+class RadioInterfaceUHD(RadioInterface):
+	def phy_init_source(self):
+		self._phy_src = uhd.usrp_source(self.phy_args,
+			uhd.stream_args(cpu_format = "fc32",
+				channels = range(1)))
+
+		self._phy_src.set_clock_rate(26e6, uhd.ALL_MBOARDS)
+		self._phy_src.set_antenna(self.rx_antenna, 0)
+		self._phy_src.set_samp_rate(self.sample_rate)
+		self._phy_src.set_bandwidth(650e3, 0)
+		self._phy_src.set_gain(self.rx_gain)
+
+		# Some UHD devices (such as UmTRX) do start the clock
+		# not from 0, so it's required to reset it manually.
+		# Resetting UHD source will also affect the sink.
+		self._phy_src.set_time_now(uhd.time_spec(0.0))
+
+	def phy_init_sink(self):
+		self._phy_sink = uhd.usrp_sink(self.phy_args,
+			uhd.stream_args(cpu_format = "fc32",
+				channels = range(1)), "packet_len")
+
+		self._phy_sink.set_clock_rate(26e6, uhd.ALL_MBOARDS)
+		self._phy_sink.set_antenna(self.tx_antenna, 0)
+		self._phy_sink.set_samp_rate(self.sample_rate)
+		self._phy_sink.set_gain(self.tx_gain)
+
+	def phy_set_rx_freq(self, freq):
+		self._phy_src.set_center_freq(freq, 0)
+
+	def phy_set_tx_freq(self, freq):
+		self._phy_sink.set_center_freq(freq, 0)
+
+	def phy_set_rx_gain(self, gain):
+		self._phy_src.set_gain(gain, 0)
+
+	def phy_set_tx_gain(self, gain):
+		self._phy_sink.set_gain(gain, 0)