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authorKévin Redon <kredon@sysmocom.de>2019-09-03 17:47:52 +0200
committerKévin Redon <kredon@sysmocom.de>2019-09-03 17:47:55 +0200
commit31f31e24eb2ad5c77bf26ea15ca45ea1940c9834 (patch)
tree502a41243f8ba8ac32f2171ae2b854e710f78cf0
parent2ad8ff810043728162593bcb820c1dec26ec41dd (diff)
schematic: mark JP1 and JP2 as dot no place
the protruding through hole pins of the header for the jumper might get shorted when the board lies on a conductive surface, leading to unwanted flash erase (JP2) or false TST signal (JP1) Change-Id: I7fc6176d8c63ab8274b641e7bcd990093af3c4ca
-rw-r--r--hardware/kicad/SIMtrace.sch4
-rw-r--r--hardware/pcb/schema/SIMtrace.pdfbin120980 -> 121120 bytes
2 files changed, 4 insertions, 0 deletions
diff --git a/hardware/kicad/SIMtrace.sch b/hardware/kicad/SIMtrace.sch
index a29e041..2baadee 100644
--- a/hardware/kicad/SIMtrace.sch
+++ b/hardware/kicad/SIMtrace.sch
@@ -827,6 +827,8 @@ F 0 "JP2" H 4500 1000 50 0000 C CNN
F 1 "ERASE" H 3800 1000 40 0000 C CNN
F 2 "PIN_ARRAY_2X1" H 4150 950 60 0001 C CNN
F 3 "" H 4150 950 60 0001 C CNN
+F 4 "NP" H 4150 1000 50 0000 C CNN "Place"
+F 5 "the pertruding through pins might get shorted when the board lies on a conductive surface, leading to unwanted flash erase" H 4150 950 50 0001 C CNN "Note"
1 4150 950
-1 0 0 -1
$EndComp
@@ -838,6 +840,8 @@ F 0 "JP1" H 3800 1100 50 0000 C CNN
F 1 "TEST" H 4500 1100 40 0000 C CNN
F 2 "PIN_ARRAY_2X1" H 4150 1050 60 0001 C CNN
F 3 "" H 4150 1050 60 0001 C CNN
+F 4 "NP" H 4150 1100 50 0000 C CNN "Place"
+F 5 "the pertruding through pins might get shorted when the board lies on a conductive surface, leading to false signal" H 4150 1050 50 0001 C CNN "Note"
1 4150 1050
1 0 0 -1
$EndComp
diff --git a/hardware/pcb/schema/SIMtrace.pdf b/hardware/pcb/schema/SIMtrace.pdf
index a6532d7..7371671 100644
--- a/hardware/pcb/schema/SIMtrace.pdf
+++ b/hardware/pcb/schema/SIMtrace.pdf
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