diff options
| -rw-r--r-- | pySim/commands.py | 3 | ||||
| -rw-r--r-- | pySim/transport/pcsc.py | 3 | ||||
| -rw-r--r-- | pySim/transport/serial.py | 15 |
3 files changed, 19 insertions, 2 deletions
diff --git a/pySim/commands.py b/pySim/commands.py index 777dd24..eba915c 100644 --- a/pySim/commands.py +++ b/pySim/commands.py @@ -31,6 +31,9 @@ class SimCardCommands(object): self._cla_byte = "a0" self.sel_ctrl = "0000" + def get_atr(self): + return self._tp.get_atr() + @property def cla_byte(self): return self._cla_byte diff --git a/pySim/transport/pcsc.py b/pySim/transport/pcsc.py index dc040c5..47c4185 100644 --- a/pySim/transport/pcsc.py +++ b/pySim/transport/pcsc.py @@ -56,6 +56,9 @@ class PcscSimLink(LinkBase): except NoCardException: raise NoCardError() + def get_atr(self): + return self._con.getATR() + def disconnect(self): self._con.disconnect() diff --git a/pySim/transport/serial.py b/pySim/transport/serial.py index 825c458..5b15b2f 100644 --- a/pySim/transport/serial.py +++ b/pySim/transport/serial.py @@ -46,6 +46,7 @@ class SerialSimLink(LinkBase): ) self._rst_pin = rst self._debug = debug + self._atr = None def __del__(self): self._sl.close() @@ -91,6 +92,9 @@ class SerialSimLink(LinkBase): def connect(self): self.reset_card() + def get_atr(self): + return self._atr + def disconnect(self): pass # Nothing to do really ... @@ -102,6 +106,7 @@ class SerialSimLink(LinkBase): raise ProtocolError() def _reset_card(self): + self._atr = None rst_meth_map = { 'rts': self._sl.setRTS, 'dtr': self._sl.setDTR, @@ -133,18 +138,24 @@ class SerialSimLink(LinkBase): return -1 t0 = ord(b) self._dbg_print("T0: 0x%x" % t0) + self._atr = [0x3b, ord(b)] for i in range(4): if t0 & (0x10 << i): - self._dbg_print("T%si = %x" % (chr(ord('A')+i), ord(self._rx_byte()))) + b = self._rx_byte() + self._atr.apend(ord(b)) + self._dbg_print("T%si = %x" % (chr(ord('A')+i), ord(b))) for i in range(0, t0 & 0xf): - self._dbg_print("Historical = %x" % ord(self._rx_byte())) + b = self._rx_byte() + self._atr.apend(ord(b)) + self._dbg_print("Historical = %x" % ord(b)) while True: x = self._rx_byte() if not x: break + self._atr.apend(ord(x)) self._dbg_print("Extra: %x" % ord(x)) return 1 |