From e74c5212b587b1a6e0154b60d3cf7d4e122de071 Mon Sep 17 00:00:00 2001 From: Mychaela Falconia Date: Mon, 11 Feb 2019 21:27:39 +0700 Subject: firmware/board/pirelli_dpl10: fix ASIC_CONF_REG setting Set LPG and PWL pin mux like Pirelli's firmware does. Change-Id: I099e13800b7821a8fb274c5264c9823153afe564 --- src/target/firmware/board/pirelli_dpl10/init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/target/firmware/board/pirelli_dpl10/init.c b/src/target/firmware/board/pirelli_dpl10/init.c index 4c74a6d3..da233088 100644 --- a/src/target/firmware/board/pirelli_dpl10/init.c +++ b/src/target/firmware/board/pirelli_dpl10/init.c @@ -60,8 +60,8 @@ static void board_io_init(void) uint16_t reg; reg = readw(ASIC_CONF_REG); - /* Set function pins to I2C Mode */ - reg |= ((1 << 12) | (1 << 7)); /* SCL / SDA */ + /* Set LPG and PWL pin mux like Pirelli's fw does */ + reg |= (1 << 6) | (1 << 4); /* TWL3025: Set SPI+RIF RX clock to rising edge */ reg |= (1 << 13) | (1 << 14); reg &= ~(1 << 1); -- cgit v1.2.3