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path: root/src/host/trxcon/trxcon.c
AgeCommit message (Expand)AuthorFilesLines
2018-03-01trxcon: Fix '-i' to specify the "TRX IP address"Harald Welte1-1/+1
2018-02-28trxcon: Define event names for osmo_fsm'sHarald Welte1-0/+9
2018-02-23trxcon|fake_trx: change default TRX port number to 6700Harald Welte1-2/+2
2017-11-23host/trxcon/scheduler: process frames in advanceVadim Yanitskiy1-2/+9
2017-11-19host/trxcon/scheduler: optionally reset clock counterVadim Yanitskiy1-2/+2
2017-11-19host/trxcon: get rid of useless TRX_EVENT_RESET_INDVadim Yanitskiy1-2/+0
2017-11-19host/trxcon: don't flush trx control messages on resetVadim Yanitskiy1-1/+1
2017-11-19host/trxcon: get rid of useless trxcon fsm eventsVadim Yanitskiy1-5/+1
2017-11-19host/trxcon: reset scheduler when L1CTL is lostVadim Yanitskiy1-0/+3
2017-11-19host/trxcon: send L1CTL_DATA_IND directly from lchan handlerVadim Yanitskiy1-4/+1
2017-11-19host/trxcon: handle L1CTL_RESET_REQ inside l1ctl.cVadim Yanitskiy1-10/+2
2017-11-19host/trxcon: handle L1CTL_FBSB_REQ inside l1ctl.cVadim Yanitskiy1-29/+0
2017-11-19host/trxcon: bind L1CTL link with TRX and vice versaVadim Yanitskiy1-0/+4
2017-11-19host/trxcon/scheduler: implement xCCH decodingVadim Yanitskiy1-1/+4
2017-11-19host/trxcon: handle ccch_mode from L1CTL_FBSB_REQVadim Yanitskiy1-4/+28
2017-11-19host/trxcon: store arfcn and band in trx_instanceVadim Yanitskiy1-5/+5
2017-11-19host/trxcon/scheduler: implement management functionsVadim Yanitskiy1-0/+10
2017-11-19host/trxcon/scheduler: add basic clock counterVadim Yanitskiy1-1/+5
2017-11-19host/trxcon: initial release of L1CTL handlersVadim Yanitskiy1-0/+18
2017-11-19host/trxcon: integrate osmo-fsm frameworkVadim Yanitskiy1-0/+66
2017-11-19host/trxcon: initial release of transceiver interfaceVadim Yanitskiy1-0/+9
2017-11-19host/trxcon: initial release of L1CTL interfaceVadim Yanitskiy1-5/+14
2017-11-19host/trxcon: introduce a new 'trxcon' applicationVadim Yanitskiy1-0/+193
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