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authorVadim Yanitskiy <axilirator@gmail.com>2019-05-30 18:48:25 +0700
committerVadim Yanitskiy <axilirator@gmail.com>2019-05-31 16:51:44 +0000
commit3655350992669ace59392d0cf185ecd4c7996ba8 (patch)
treec0450fd82997800b431ac401908e3710697f9540 /src
parent49bec6c4783522955985b0603fba949a4bafe19b (diff)
trxcon/sched_mframe.c: mark all stolen CBCH UL slots as TRXC_IDLE
According to 3GPP TS 05.02, section 6.4.1, CBCH replaces SDCCH number 2 in both V (BCCH+CCCH+SDCCH/4+SACCH/4) and VII (SDCCH/8+SACCH/8) logical channel combinations. Unfortunately it is not clear whether we can use stolen UL slots for RACH or not. For now, we should mark all of them as IDLE. Somehow TRXC_SDCCH4_2 slots were left in the definition of combination V (combined CCCH+BCCH). This is not critical, but may be looking confusing. Let's fix this. Change-Id: Id30f2fac3274de3edff4ae59f77d9c9cf8059155
Diffstat (limited to 'src')
-rw-r--r--src/host/trxcon/sched_mframe.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/host/trxcon/sched_mframe.c b/src/host/trxcon/sched_mframe.c
index d427993a..9b759af3 100644
--- a/src/host/trxcon/sched_mframe.c
+++ b/src/host/trxcon/sched_mframe.c
@@ -292,10 +292,10 @@ static const struct trx_frame frame_bcch_sdcch4_cbch[102] = {
{ TRXC_IDLE, 2, TRXC_SDCCH4_1, 3 },
{ TRXC_IDLE, 3, TRXC_RACH, 0 },
{ TRXC_SACCH4_3, 0, TRXC_RACH, 0 },
- { TRXC_SACCH4_3, 1, TRXC_SDCCH4_2, 0 },
- { TRXC_SACCH4_3, 2, TRXC_SDCCH4_2, 1 },
- { TRXC_SACCH4_3, 3, TRXC_SDCCH4_2, 2 },
- { TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },
+ { TRXC_SACCH4_3, 1, TRXC_IDLE, 0 },
+ { TRXC_SACCH4_3, 2, TRXC_IDLE, 1 },
+ { TRXC_SACCH4_3, 3, TRXC_IDLE, 2 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 3 },
};
static const struct trx_frame frame_sdcch8[102] = {