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authorMychaela Falconia <mychaela.falconia@gmail.com>2019-02-11 21:27:39 +0700
committerVadim Yanitskiy <axilirator@gmail.com>2019-02-12 01:05:30 +0700
commite74c5212b587b1a6e0154b60d3cf7d4e122de071 (patch)
tree046d8bbdcf880fc8bf71999d1e4042b5d4a5c99d /src/target
parent1c6263b2be90b3916471a37c2ff323fc725dfc92 (diff)
firmware/board/pirelli_dpl10: fix ASIC_CONF_REG setting
Set LPG and PWL pin mux like Pirelli's firmware does. Change-Id: I099e13800b7821a8fb274c5264c9823153afe564
Diffstat (limited to 'src/target')
-rw-r--r--src/target/firmware/board/pirelli_dpl10/init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/firmware/board/pirelli_dpl10/init.c b/src/target/firmware/board/pirelli_dpl10/init.c
index 4c74a6d3..da233088 100644
--- a/src/target/firmware/board/pirelli_dpl10/init.c
+++ b/src/target/firmware/board/pirelli_dpl10/init.c
@@ -60,8 +60,8 @@ static void board_io_init(void)
uint16_t reg;
reg = readw(ASIC_CONF_REG);
- /* Set function pins to I2C Mode */
- reg |= ((1 << 12) | (1 << 7)); /* SCL / SDA */
+ /* Set LPG and PWL pin mux like Pirelli's fw does */
+ reg |= (1 << 6) | (1 << 4);
/* TWL3025: Set SPI+RIF RX clock to rising edge */
reg |= (1 << 13) | (1 << 14);
reg &= ~(1 << 1);