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authorSylvain Munaut <tnt@246tNt.com>2010-10-30 21:13:41 +0200
committerSylvain Munaut <tnt@246tNt.com>2010-11-07 10:34:09 +0100
commit375f41a9dd1fc50a79295b6a64470bab61eb19b3 (patch)
treee74435498f7b48151fd1f5ad293fcd427ed384b3 /src/target/firmware/layer1/mframe_sched.c
parent2ac17ed9fa6b44dbfa3dfb91dd6981319c7363c0 (diff)
target/fw/l1: Fix TCH/H by properly scheduling the TCHD task during 'off' slots
Apparently the DSP needs to be run even during the slots without actual bursts exchange. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'src/target/firmware/layer1/mframe_sched.c')
-rw-r--r--src/target/firmware/layer1/mframe_sched.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/target/firmware/layer1/mframe_sched.c b/src/target/firmware/layer1/mframe_sched.c
index 30cd03f7..2a884d7c 100644
--- a/src/target/firmware/layer1/mframe_sched.c
+++ b/src/target/firmware/layer1/mframe_sched.c
@@ -200,6 +200,7 @@ static const struct mframe_sched_item mf_sdcch8_7[] = {
/* TCH */
#define TCH tch_sched_set
#define TCH_A tch_a_sched_set
+#define TCH_D tch_d_sched_set
static const struct mframe_sched_item mf_tch_f_even[] = {
{ .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
@@ -237,21 +238,33 @@ static const struct mframe_sched_item mf_tch_f_odd[] = {
static const struct mframe_sched_item mf_tch_h_0[] = {
{ .sched_set = TCH, .modulo = 13, .frame_nr = 0 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 1 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 2 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 3 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 4 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 5 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 6 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 7 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 8 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 9 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 10 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 11 },
{ .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
{ .sched_set = NULL }
};
static const struct mframe_sched_item mf_tch_h_1[] = {
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 0 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 1 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 2 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 3 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 4 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 5 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 6 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 7 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 8 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 9 },
+ { .sched_set = TCH_D, .modulo = 13, .frame_nr = 10 },
{ .sched_set = TCH, .modulo = 13, .frame_nr = 11 },
{ .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
{ .sched_set = NULL }