diff options
| author | Andreas.Eversberg <jolly@eversberg.eu> | 2010-07-13 14:07:37 +0000 |
|---|---|---|
| committer | Andreas.Eversberg <jolly@eversberg.eu> | 2010-07-13 14:07:37 +0000 |
| commit | c6ff4723ce112a6de77aacaf89e73fe4b4c7c278 (patch) | |
| tree | 0193cad52fe0c1fc0be70f4017738e45bfa8ff74 /src/target/firmware/include/layer1/sync.h | |
| parent | 9a422ceb257559b0264cd306489fab0b854b96bc (diff) | |
[layer 1] L1CTL_PARAM_REQ is introduced to change TX power and TA.
Currently only TA (timing advance) is supported. It ranges from -128 to 128.
Diffstat (limited to 'src/target/firmware/include/layer1/sync.h')
| -rw-r--r-- | src/target/firmware/include/layer1/sync.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/firmware/include/layer1/sync.h b/src/target/firmware/include/layer1/sync.h index 760b44ce..76134497 100644 --- a/src/target/firmware/include/layer1/sync.h +++ b/src/target/firmware/include/layer1/sync.h @@ -60,6 +60,8 @@ struct l1s_state { /* The current TPU offset register */ uint32_t tpu_offset; + int8_t ta; + /* Transmit queues of pending packets for main DCCH and ACCH */ struct llist_head tx_queue[_NUM_L1S_CHAN]; |