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authorVadim Yanitskiy <axilirator@gmail.com>2017-07-04 19:38:50 +0700
committerVadim Yanitskiy <axilirator@gmail.com>2017-10-23 22:05:49 +0330
commitac1531cd92b49353ca5850609d45233c32d139ea (patch)
tree4550bbd9704f940cf55a6e99542cdacb2481bc85
parent2637b084011859c034d6447c789871ac08d2ba34 (diff)
host/trxcon/scheduler: add basic GSM PHY definitions
-rw-r--r--src/host/trxcon/Makefile.am2
-rw-r--r--src/host/trxcon/sched_lchan_desc.c281
-rw-r--r--src/host/trxcon/sched_mframe.c1814
-rw-r--r--src/host/trxcon/sched_trx.h235
4 files changed, 2332 insertions, 0 deletions
diff --git a/src/host/trxcon/Makefile.am b/src/host/trxcon/Makefile.am
index de120297..a5008e6f 100644
--- a/src/host/trxcon/Makefile.am
+++ b/src/host/trxcon/Makefile.am
@@ -30,6 +30,8 @@ trxcon_SOURCES = \
# Scheduler
trxcon_SOURCES += \
+ sched_lchan_desc.c \
+ sched_mframe.c \
sched_clck.c \
$(NULL)
diff --git a/src/host/trxcon/sched_lchan_desc.c b/src/host/trxcon/sched_lchan_desc.c
new file mode 100644
index 00000000..880c2a59
--- /dev/null
+++ b/src/host/trxcon/sched_lchan_desc.c
@@ -0,0 +1,281 @@
+/*
+ * OsmocomBB <-> SDR connection bridge
+ * TDMA scheduler: logical channels, RX / TX handlers
+ *
+ * (C) 2013 by Andreas Eversberg <jolly@eversberg.eu>
+ * (C) 2015 by Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
+ * (C) 2015 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Affero General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Affero General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "sched_trx.h"
+
+#define LID_DEDIC 0x00
+#define LID_SACCH 0x40
+
+/* TODO: implement */
+#define tx_data_fn NULL
+#define tx_pdtch_fn NULL
+#define tx_tchf_fn NULL
+#define tx_tchh_fn NULL
+#define tx_rach_fn NULL
+
+#define rx_data_fn NULL
+#define rx_pdtch_fn NULL
+#define rx_tchf_fn NULL
+#define rx_tchh_fn NULL
+
+const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX] = {
+ {
+ TRXC_IDLE, "IDLE",
+ 0x00, LID_DEDIC,
+ 0x00, 0x00,
+
+ /**
+ * MS: do nothing, save power...
+ * BTS: send dummy burst on C0
+ */
+ NULL, NULL,
+ },
+ {
+ TRXC_FCCH, "FCCH",
+ 0x00, LID_DEDIC,
+ 0x00, 0x00,
+
+ /* FCCH is handled by transceiver */
+ NULL, NULL,
+ },
+ {
+ TRXC_SCH, "SCH",
+ 0x00, LID_DEDIC,
+ 0x00, 0x00,
+
+ /* We already have clock indications from TRX */
+ NULL, NULL,
+ },
+ {
+ TRXC_BCCH, "BCCH",
+ 0x80, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, TRX_CH_FLAG_AUTO,
+ rx_data_fn, NULL,
+ },
+ {
+ TRXC_RACH, "RACH",
+ 0x88, LID_DEDIC,
+ 0x00, TRX_CH_FLAG_AUTO,
+ NULL, tx_rach_fn,
+ },
+ {
+ TRXC_CCCH, "CCCH",
+ 0x90, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, TRX_CH_FLAG_AUTO,
+ rx_data_fn, NULL,
+ },
+ {
+ TRXC_TCHF, "TCH/F",
+ 0x08, LID_DEDIC,
+ 8 * GSM_BURST_PL_LEN, 0x00,
+ rx_tchf_fn, tx_tchf_fn,
+ },
+ {
+ TRXC_TCHH_0, "TCH/H(0)",
+ 0x10, LID_DEDIC,
+ 6 * GSM_BURST_PL_LEN, 0x00,
+ rx_tchh_fn, tx_tchh_fn,
+ },
+ {
+ TRXC_TCHH_1, "TCH/H(1)",
+ 0x18, LID_DEDIC,
+ 6 * GSM_BURST_PL_LEN, 0x00,
+ rx_tchh_fn, tx_tchh_fn,
+ },
+ {
+ TRXC_SDCCH4_0, "SDCCH/4(0)",
+ 0x20, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH4_1, "SDCCH/4(1)",
+ 0x28, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH4_2, "SDCCH/4(2)",
+ 0x30, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH4_3, "SDCCH/4(3)",
+ 0x38, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_0, "SDCCH/8(0)",
+ 0x40, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_1, "SDCCH/8(1)",
+ 0x48, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_2, "SDCCH/8(2)",
+ 0x50, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_3, "SDCCH/8(3)",
+ 0x58, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_4, "SDCCH/8(4)",
+ 0x60, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_5, "SDCCH/8(5)",
+ 0x68, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_6, "SDCCH/8(6)",
+ 0x70, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SDCCH8_7, "SDCCH/8(7)",
+ 0x78, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCHTF, "SACCH/TF",
+ 0x08, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCHTH_0, "SACCH/TH(0)",
+ 0x10, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCHTH_1, "SACCH/TH(1)",
+ 0x18, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH4_0, "SACCH/4(0)",
+ 0x20, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH4_1, "SACCH/4(1)",
+ 0x28, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH4_2, "SACCH/4(2)",
+ 0x30, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH4_3, "SACCH/4(3)",
+ 0x38, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_0, "SACCH/8(0)",
+ 0x40, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_1, "SACCH/8(1)",
+ 0x48, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_2, "SACCH/8(2)",
+ 0x50, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_3, "SACCH/8(3)",
+ 0x58, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_4, "SACCH/8(4)",
+ 0x60, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_5, "SACCH/8(5)",
+ 0x68, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_6, "SACCH/8(6)",
+ 0x70, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_SACCH8_7, "SACCH/8(7)",
+ 0x78, LID_SACCH,
+ 4 * GSM_BURST_PL_LEN, 0x00,
+ rx_data_fn, tx_data_fn,
+ },
+ {
+ TRXC_PDTCH, "PDTCH",
+ 0x08, LID_DEDIC,
+ 12 * GSM_BURST_PL_LEN, TRX_CH_FLAG_PDCH,
+ rx_pdtch_fn, tx_pdtch_fn,
+ },
+ {
+ TRXC_PTCCH, "PTCCH",
+ 0x08, LID_DEDIC,
+ 4 * GSM_BURST_PL_LEN, TRX_CH_FLAG_PDCH,
+ rx_data_fn, tx_data_fn,
+ },
+};
diff --git a/src/host/trxcon/sched_mframe.c b/src/host/trxcon/sched_mframe.c
new file mode 100644
index 00000000..5f9d78fd
--- /dev/null
+++ b/src/host/trxcon/sched_mframe.c
@@ -0,0 +1,1814 @@
+/*
+ * OsmocomBB <-> SDR connection bridge
+ * TDMA scheduler: channel combinations, burst mapping
+ *
+ * (C) 2013 by Andreas Eversberg <jolly@eversberg.eu>
+ * (C) 2015 by Alexander Chemeris <Alexander.Chemeris@fairwaves.co>
+ * (C) 2015 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Affero General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Affero General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <osmocom/gsm/gsm_utils.h>
+
+#include "sched_trx.h"
+
+/* Non-combined CCCH */
+static const struct trx_frame frame_bcch[51] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_BCCH, 0, TRXC_RACH, 0 },
+ { TRXC_BCCH, 1, TRXC_RACH, 0 },
+ { TRXC_BCCH, 2, TRXC_RACH, 0 },
+ { TRXC_BCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_IDLE, 0, TRXC_RACH, 0 },
+};
+
+/* Combined CCCH+SDCCH4 */
+static const struct trx_frame frame_bcch_sdcch4[102] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
+ { TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
+ { TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
+ { TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
+ { TRXC_BCCH, 2, TRXC_RACH, 0 },
+ { TRXC_BCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_SACCH4_2, 0 },
+ { TRXC_CCCH, 1, TRXC_SACCH4_2, 1 },
+ { TRXC_CCCH, 2, TRXC_SACCH4_2, 2 },
+ { TRXC_CCCH, 3, TRXC_SACCH4_2, 3 },
+ { TRXC_FCCH, 0, TRXC_SACCH4_3, 0 },
+ { TRXC_SCH, 0, TRXC_SACCH4_3, 1 },
+ { TRXC_CCCH, 0, TRXC_SACCH4_3, 2 },
+ { TRXC_CCCH, 1, TRXC_SACCH4_3, 3 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 3, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
+ { TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
+ { TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
+ { TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
+ { TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
+ { TRXC_SACCH4_0, 0, TRXC_SDCCH4_1, 1 },
+ { TRXC_SACCH4_0, 1, TRXC_SDCCH4_1, 2 },
+ { TRXC_SACCH4_0, 2, TRXC_SDCCH4_1, 3 },
+ { TRXC_SACCH4_0, 3, TRXC_RACH, 0 },
+ { TRXC_SACCH4_1, 0, TRXC_RACH, 0 },
+ { TRXC_SACCH4_1, 1, TRXC_SDCCH4_2, 0 },
+ { TRXC_SACCH4_1, 2, TRXC_SDCCH4_2, 1 },
+ { TRXC_SACCH4_1, 3, TRXC_SDCCH4_2, 2 },
+ { TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },
+
+ { TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },
+ { TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },
+ { TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },
+ { TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },
+ { TRXC_BCCH, 2, TRXC_RACH, 0 },
+ { TRXC_BCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_SACCH4_0, 0 },
+ { TRXC_CCCH, 1, TRXC_SACCH4_0, 1 },
+ { TRXC_CCCH, 2, TRXC_SACCH4_0, 2 },
+ { TRXC_CCCH, 3, TRXC_SACCH4_0, 3 },
+ { TRXC_FCCH, 0, TRXC_SACCH4_1, 0 },
+ { TRXC_SCH, 0, TRXC_SACCH4_1, 1 },
+ { TRXC_CCCH, 0, TRXC_SACCH4_1, 2 },
+ { TRXC_CCCH, 1, TRXC_SACCH4_1, 3 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_CCCH, 0, TRXC_RACH, 0 },
+ { TRXC_CCCH, 1, TRXC_RACH, 0 },
+ { TRXC_CCCH, 2, TRXC_RACH, 0 },
+ { TRXC_CCCH, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },
+ { TRXC_FCCH, 0, TRXC_RACH, 0 },
+ { TRXC_SCH, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 1, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 2, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_2, 3, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },
+ { TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },
+ { TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },
+ { TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },
+ { TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },
+ { TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },
+ { TRXC_SACCH4_2, 0, TRXC_SDCCH4_1, 1 },
+ { TRXC_SACCH4_2, 1, TRXC_SDCCH4_1, 2 },
+ { TRXC_SACCH4_2, 2, TRXC_SDCCH4_1, 3 },
+ { TRXC_SACCH4_2, 3, TRXC_RACH, 0 },
+ { TRXC_SACCH4_3, 0, TRXC_RACH, 0 },
+ { TRXC_SACCH4_3, 1, TRXC_SDCCH4_2, 0 },
+ { TRXC_SACCH4_3, 2, TRXC_SDCCH4_2, 1 },
+ { TRXC_SACCH4_3, 3, TRXC_SDCCH4_2, 2 },
+ { TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },
+};
+
+static const struct trx_frame frame_sdcch8[102] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_SDCCH8_0, 0, TRXC_SACCH8_5, 0 },
+ { TRXC_SDCCH8_0, 1, TRXC_SACCH8_5, 1 },
+ { TRXC_SDCCH8_0, 2, TRXC_SACCH8_5, 2 },
+ { TRXC_SDCCH8_0, 3, TRXC_SACCH8_5, 3 },
+ { TRXC_SDCCH8_1, 0, TRXC_SACCH8_6, 0 },
+ { TRXC_SDCCH8_1, 1, TRXC_SACCH8_6, 1 },
+ { TRXC_SDCCH8_1, 2, TRXC_SACCH8_6, 2 },
+ { TRXC_SDCCH8_1, 3, TRXC_SACCH8_6, 3 },
+ { TRXC_SDCCH8_2, 0, TRXC_SACCH8_7, 0 },
+ { TRXC_SDCCH8_2, 1, TRXC_SACCH8_7, 1 },
+ { TRXC_SDCCH8_2, 2, TRXC_SACCH8_7, 2 },
+ { TRXC_SDCCH8_2, 3, TRXC_SACCH8_7, 3 },
+ { TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
+ { TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
+ { TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
+ { TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
+ { TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
+ { TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
+ { TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
+ { TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
+ { TRXC_SDCCH8_5, 3, TRXC_SDCCH8_2, 0 },
+ { TRXC_SDCCH8_6, 0, TRXC_SDCCH8_2, 1 },
+ { TRXC_SDCCH8_6, 1, TRXC_SDCCH8_2, 2 },
+ { TRXC_SDCCH8_6, 2, TRXC_SDCCH8_2, 3 },
+ { TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
+ { TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
+ { TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
+ { TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
+ { TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
+ { TRXC_SACCH8_0, 0, TRXC_SDCCH8_4, 1 },
+ { TRXC_SACCH8_0, 1, TRXC_SDCCH8_4, 2 },
+ { TRXC_SACCH8_0, 2, TRXC_SDCCH8_4, 3 },
+ { TRXC_SACCH8_0, 3, TRXC_SDCCH8_5, 0 },
+ { TRXC_SACCH8_1, 0, TRXC_SDCCH8_5, 1 },
+ { TRXC_SACCH8_1, 1, TRXC_SDCCH8_5, 2 },
+ { TRXC_SACCH8_1, 2, TRXC_SDCCH8_5, 3 },
+ { TRXC_SACCH8_1, 3, TRXC_SDCCH8_6, 0 },
+ { TRXC_SACCH8_2, 0, TRXC_SDCCH8_6, 1 },
+ { TRXC_SACCH8_2, 1, TRXC_SDCCH8_6, 2 },
+ { TRXC_SACCH8_2, 2, TRXC_SDCCH8_6, 3 },
+ { TRXC_SACCH8_2, 3, TRXC_SDCCH8_7, 0 },
+ { TRXC_SACCH8_3, 0, TRXC_SDCCH8_7, 1 },
+ { TRXC_SACCH8_3, 1, TRXC_SDCCH8_7, 2 },
+ { TRXC_SACCH8_3, 2, TRXC_SDCCH8_7, 3 },
+ { TRXC_SACCH8_3, 3, TRXC_SACCH8_0, 0 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 1 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 2 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 3 },
+
+ { TRXC_SDCCH8_0, 0, TRXC_SACCH8_1, 0 },
+ { TRXC_SDCCH8_0, 1, TRXC_SACCH8_1, 1 },
+ { TRXC_SDCCH8_0, 2, TRXC_SACCH8_1, 2 },
+ { TRXC_SDCCH8_0, 3, TRXC_SACCH8_1, 3 },
+ { TRXC_SDCCH8_1, 0, TRXC_SACCH8_2, 0 },
+ { TRXC_SDCCH8_1, 1, TRXC_SACCH8_2, 1 },
+ { TRXC_SDCCH8_1, 2, TRXC_SACCH8_2, 2 },
+ { TRXC_SDCCH8_1, 3, TRXC_SACCH8_2, 3 },
+ { TRXC_SDCCH8_2, 0, TRXC_SACCH8_3, 0 },
+ { TRXC_SDCCH8_2, 1, TRXC_SACCH8_3, 1 },
+ { TRXC_SDCCH8_2, 2, TRXC_SACCH8_3, 2 },
+ { TRXC_SDCCH8_2, 3, TRXC_SACCH8_3, 3 },
+ { TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },
+ { TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },
+ { TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },
+ { TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },
+ { TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },
+ { TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },
+ { TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },
+ { TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },
+ { TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },
+ { TRXC_SDCCH8_5, 3, TRXC_SDCCH8_2, 0 },
+ { TRXC_SDCCH8_6, 0, TRXC_SDCCH8_2, 1 },
+ { TRXC_SDCCH8_6, 1, TRXC_SDCCH8_2, 2 },
+ { TRXC_SDCCH8_6, 2, TRXC_SDCCH8_2, 3 },
+ { TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },
+ { TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },
+ { TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },
+ { TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },
+ { TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },
+ { TRXC_SACCH8_4, 0, TRXC_SDCCH8_4, 1 },
+ { TRXC_SACCH8_4, 1, TRXC_SDCCH8_4, 2 },
+ { TRXC_SACCH8_4, 2, TRXC_SDCCH8_4, 3 },
+ { TRXC_SACCH8_4, 3, TRXC_SDCCH8_5, 0 },
+ { TRXC_SACCH8_5, 0, TRXC_SDCCH8_5, 1 },
+ { TRXC_SACCH8_5, 1, TRXC_SDCCH8_5, 2 },
+ { TRXC_SACCH8_5, 2, TRXC_SDCCH8_5, 3 },
+ { TRXC_SACCH8_5, 3, TRXC_SDCCH8_6, 0 },
+ { TRXC_SACCH8_6, 0, TRXC_SDCCH8_6, 1 },
+ { TRXC_SACCH8_6, 1, TRXC_SDCCH8_6, 2 },
+ { TRXC_SACCH8_6, 2, TRXC_SDCCH8_6, 3 },
+ { TRXC_SACCH8_6, 3, TRXC_SDCCH8_7, 0 },
+ { TRXC_SACCH8_7, 0, TRXC_SDCCH8_7, 1 },
+ { TRXC_SACCH8_7, 1, TRXC_SDCCH8_7, 2 },
+ { TRXC_SACCH8_7, 2, TRXC_SDCCH8_7, 3 },
+ { TRXC_SACCH8_7, 3, TRXC_SACCH8_4, 0 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 1 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 2 },
+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 3 },
+};
+
+static const struct trx_frame frame_tchf_ts0[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+};
+
+static const struct trx_frame frame_tchf_ts1[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+};
+
+static const struct trx_frame frame_tchf_ts2[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+};
+
+static const struct trx_frame frame_tchf_ts3[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+};
+
+static const struct trx_frame frame_tchf_ts4[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+};
+
+static const struct trx_frame frame_tchf_ts5[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+};
+
+static const struct trx_frame frame_tchf_ts6[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+};
+
+static const struct trx_frame frame_tchf_ts7[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 1, TRXC_SACCHTF, 1 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 2, TRXC_SACCHTF, 2 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 3, TRXC_SACCHTF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_TCHF, 0, TRXC_TCHF, 0 },
+ { TRXC_TCHF, 1, TRXC_TCHF, 1 },
+ { TRXC_TCHF, 2, TRXC_TCHF, 2 },
+ { TRXC_TCHF, 3, TRXC_TCHF, 3 },
+ { TRXC_SACCHTF, 0, TRXC_SACCHTF, 0 },
+};
+
+static const struct trx_frame frame_tchh_ts01[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
+};
+
+static const struct trx_frame frame_tchh_ts23[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
+};
+
+static const struct trx_frame frame_tchh_ts45[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
+};
+
+static const struct trx_frame frame_tchh_ts67[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 1, TRXC_SACCHTH_0, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 1, TRXC_SACCHTH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 2, TRXC_SACCHTH_0, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 2, TRXC_SACCHTH_1, 2 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 3, TRXC_SACCHTH_0, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 3, TRXC_SACCHTH_1, 3 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_0, 0, TRXC_SACCHTH_0, 0 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_TCHH_0, 0, TRXC_TCHH_0, 0 },
+ { TRXC_TCHH_1, 0, TRXC_TCHH_1, 0 },
+ { TRXC_TCHH_0, 1, TRXC_TCHH_0, 1 },
+ { TRXC_TCHH_1, 1, TRXC_TCHH_1, 1 },
+ { TRXC_SACCHTH_1, 0, TRXC_SACCHTH_1, 0 },
+};
+
+static const struct trx_frame frame_pdch[104] = {
+ /* dl_chan dl_bid ul_chan ul_bid */
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PTCCH, 0, TRXC_PTCCH, 0 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PTCCH, 1, TRXC_PTCCH, 1 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PTCCH, 2, TRXC_PTCCH, 2 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PTCCH, 3, TRXC_PTCCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_PDTCH, 0, TRXC_PDTCH, 0 },
+ { TRXC_PDTCH, 1, TRXC_PDTCH, 1 },
+ { TRXC_PDTCH, 2, TRXC_PDTCH, 2 },
+ { TRXC_PDTCH, 3, TRXC_PDTCH, 3 },
+ { TRXC_IDLE, 0, TRXC_IDLE, 0 },
+};
+
+/**
+ * A few notes about frame count:
+ *
+ * 26 frame multiframe - traffic multiframe
+ * 51 frame multiframe - control multiframe
+ *
+ * 102 = 2 x 51 frame multiframe
+ * 104 = 4 x 26 frame multiframe
+ */
+static const struct trx_multiframe layouts[] = {
+ {
+ GSM_PCHAN_NONE, "NONE",
+ 0, 0xff, (uint64_t) 0x00,
+ NULL
+ },
+ {
+ GSM_PCHAN_CCCH, "BCCH+CCCH",
+ 51, 0xff, (uint64_t) 0x3e,
+ frame_bcch
+ },
+ {
+ GSM_PCHAN_CCCH_SDCCH4, "BCCH+CCCH+SDCCH/4+SACCH/4",
+ 102, 0xff, (uint64_t) 0xf001e3e,
+ frame_bcch_sdcch4
+ },
+ {
+ GSM_PCHAN_SDCCH8_SACCH8C, "SDCCH/8+SACCH/8",
+ 102, 0xff, (uint64_t) 0xff01fe000,
+ frame_sdcch8
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x01, (uint64_t) 0x200040,
+ frame_tchf_ts0
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x02, (uint64_t) 0x200040,
+ frame_tchf_ts1
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x04, (uint64_t) 0x200040,
+ frame_tchf_ts2
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x08, (uint64_t) 0x200040,
+ frame_tchf_ts3
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x10, (uint64_t) 0x200040,
+ frame_tchf_ts4
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x20, (uint64_t) 0x200040,
+ frame_tchf_ts5
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x40, (uint64_t) 0x200040,
+ frame_tchf_ts6
+ },
+ {
+ GSM_PCHAN_TCH_F, "TCH/F+SACCH",
+ 104, 0x80, (uint64_t) 0x200040,
+ frame_tchf_ts7
+ },
+ {
+ GSM_PCHAN_TCH_H, "TCH/H+SACCH",
+ 104, 0x03, (uint64_t) 0xc00180,
+ frame_tchh_ts01
+ },
+ {
+ GSM_PCHAN_TCH_H, "TCH/H+SACCH",
+ 104, 0x0c, (uint64_t) 0xc00180,
+ frame_tchh_ts23
+ },
+ {
+ GSM_PCHAN_TCH_H, "TCH/H+SACCH",
+ 104, 0x30, (uint64_t) 0xc00180,
+ frame_tchh_ts45
+ },
+ {
+ GSM_PCHAN_TCH_H, "TCH/H+SACCH",
+ 104, 0xc0, (uint64_t) 0xc00180,
+ frame_tchh_ts67
+ },
+ {
+ GSM_PCHAN_PDCH, "PDCH",
+ 104, 0xff, (uint64_t) 0x3000000000,
+ frame_pdch
+ },
+};
+
+const struct trx_multiframe *sched_mframe_layout(
+ enum gsm_phys_chan_config config, int ts_num)
+{
+ int i, ts_allowed;
+
+ for (i = 0; i < ARRAY_SIZE(layouts); i++) {
+ ts_allowed = layouts[i].slotmask & (0x01 << ts_num);
+ if (layouts[i].chan_config == config && ts_allowed)
+ return &layouts[i];
+ }
+
+ return NULL;
+}
diff --git a/src/host/trxcon/sched_trx.h b/src/host/trxcon/sched_trx.h
new file mode 100644
index 00000000..1abd5156
--- /dev/null
+++ b/src/host/trxcon/sched_trx.h
@@ -0,0 +1,235 @@
+#pragma once
+
+#include <stdint.h>
+
+#include <osmocom/core/bits.h>
+#include <osmocom/core/utils.h>
+#include <osmocom/gsm/gsm_utils.h>
+#include <osmocom/core/linuxlist.h>
+
+#include "logging.h"
+#include "scheduler.h"
+
+#define GSM_BURST_LEN 148
+#define GSM_BURST_PL_LEN 116
+
+#define GPRS_BURST_LEN GSM_BURST_LEN
+#define EDGE_BURST_LEN 444
+
+#define TRX_CH_FLAG_PDCH (1 << 0)
+#define TRX_CH_FLAG_AUTO (1 << 1)
+#define TRX_TS_COUNT 8
+
+#define MAX_A5_KEY_LEN (128 / 8)
+
+/* Forward declaration to avoid mutual include */
+struct trx_instance;
+struct trx_ts;
+
+enum trx_burst_type {
+ TRX_BURST_GMSK,
+ TRX_BURST_8PSK,
+};
+
+/**
+ * These types define the different channels on a multiframe.
+ * Each channel has queues and can be activated individually.
+ */
+enum trx_lchan_type {
+ TRXC_IDLE = 0,
+ TRXC_FCCH,
+ TRXC_SCH,
+ TRXC_BCCH,
+ TRXC_RACH,
+ TRXC_CCCH,
+ TRXC_TCHF,
+ TRXC_TCHH_0,
+ TRXC_TCHH_1,
+ TRXC_SDCCH4_0,
+ TRXC_SDCCH4_1,
+ TRXC_SDCCH4_2,
+ TRXC_SDCCH4_3,
+ TRXC_SDCCH8_0,
+ TRXC_SDCCH8_1,
+ TRXC_SDCCH8_2,
+ TRXC_SDCCH8_3,
+ TRXC_SDCCH8_4,
+ TRXC_SDCCH8_5,
+ TRXC_SDCCH8_6,
+ TRXC_SDCCH8_7,
+ TRXC_SACCHTF,
+ TRXC_SACCHTH_0,
+ TRXC_SACCHTH_1,
+ TRXC_SACCH4_0,
+ TRXC_SACCH4_1,
+ TRXC_SACCH4_2,
+ TRXC_SACCH4_3,
+ TRXC_SACCH8_0,
+ TRXC_SACCH8_1,
+ TRXC_SACCH8_2,
+ TRXC_SACCH8_3,
+ TRXC_SACCH8_4,
+ TRXC_SACCH8_5,
+ TRXC_SACCH8_6,
+ TRXC_SACCH8_7,
+ TRXC_PDTCH,
+ TRXC_PTCCH,
+ _TRX_CHAN_MAX
+};
+
+typedef int trx_lchan_rx_func(struct trx_instance *trx,
+ struct trx_ts *ts,
+ uint32_t fn, enum trx_lchan_type chan,
+ uint8_t bid, sbit_t *bits, uint16_t nbits,
+ int8_t rssi, float toa);
+
+typedef ubit_t *trx_lchan_tx_func(struct trx_instance *trx,
+ struct trx_ts *ts,
+ uint32_t fn, enum trx_lchan_type chan,
+ uint8_t bid, uint16_t *nbits);
+
+struct trx_lchan_desc {
+ /*! \brief TRX Channel Type */
+ enum trx_lchan_type chan;
+ /*! \brief Human-readable name */
+ const char *name;
+ /*! \brief Channel Number (like in RSL) */
+ uint8_t chan_nr;
+ /*! \brief Link ID (like in RSL) */
+ uint8_t link_id;
+
+ /*! \brief How much memory do we need to store bursts */
+ size_t burst_buf_size;
+ /*! \brief Channel specific flags */
+ uint8_t flags;
+
+ /*! \brief Function to call when burst received from PHY */
+ trx_lchan_rx_func *rx_fn;
+ /*! \brief Function to call when data received from L2 */
+ trx_lchan_tx_func *tx_fn;
+};
+
+struct trx_frame {
+ /*! \brief Downlink TRX channel type */
+ enum trx_lchan_type dl_chan;
+ /*! \brief Downlink block ID */
+ uint8_t dl_bid;
+ /*! \brief Uplink TRX channel type */
+ enum trx_lchan_type ul_chan;
+ /*! \brief Uplink block ID */
+ uint8_t ul_bid;
+};
+
+struct trx_multiframe {
+ /*! \brief Channel combination */
+ enum gsm_phys_chan_config chan_config;
+ /*! \brief Human-readable name */
+ const char *name;
+ /*! \brief Repeats how many frames */
+ uint8_t period;
+ /*! \brief Applies to which timeslots */
+ uint8_t slotmask;
+ /*! \brief Contains which lchans */
+ uint64_t lchan_mask;
+ /*! \brief Pointer to scheduling structure */
+ const struct trx_frame *frames;
+};
+
+/* States each channel on a multiframe */
+struct trx_lchan_state {
+ /*! \brief Channel type */
+ enum trx_lchan_type type;
+ /*! \brief Channel status */
+ uint8_t active;
+
+ /*! \brief Burst type: GMSK or 8PSK */
+ enum trx_burst_type burst_type;
+ /*! \brief Frame number of first burst */
+ uint32_t rx_first_fn;
+ /*! \brief Mask of received bursts */
+ uint8_t rx_burst_mask;
+ /*! \brief Burst buffer for RX */
+ sbit_t *rx_bursts;
+ /*! \brief Burst buffer for TX */
+ ubit_t *tx_bursts;
+
+ /*! \brief Number of RSSI values */
+ uint8_t rssi_num;
+ /*! \brief Sum of RSSI values */
+ float rssi_sum;
+ /*! \brief Number of TOA values */
+ uint8_t toa_num;
+ /*! \brief Sum of TOA values */
+ float toa_sum;
+ /*! \brief (SACCH) loss detection */
+ uint8_t lost;
+ /*! \brief Mode for TCH channels */
+ uint8_t rsl_cmode, tch_mode;
+
+ /* AMR specific */
+ /*! \brief 4 possible codecs for AMR */
+ uint8_t codec[4];
+ /*! \brief Number of possible codecs */
+ int codecs;
+ /*! \brief Sum of bit error rates */
+ float ber_sum;
+ /*! \brief Number of bit error rates */
+ int ber_num;
+ /*! \brief Current uplink FT index */
+ uint8_t ul_ft;
+ /*! \brief Current downlink FT index */
+ uint8_t dl_ft;
+ /*! \brief Current uplink CMR index */
+ uint8_t ul_cmr;
+ /*! \brief Current downlink CMR index */
+ uint8_t dl_cmr;
+ /*! \brief If AMR loop is enabled */
+ uint8_t amr_loop;
+
+ /* TCH/H */
+ uint8_t dl_ongoing_facch; /*! \brief FACCH/H on downlink */
+ uint8_t ul_ongoing_facch; /*! \brief FACCH/H on uplink */
+
+ /*! \brief A5/x encryption algorithm */
+ int encr_algo;
+ int encr_key_len;
+ uint8_t encr_key[MAX_A5_KEY_LEN];
+
+ /*! \brief Measurements */
+ struct {
+ /*! \brief Cyclic clock counter */
+ uint8_t clock;
+ /*! \brief Last RSSI values */
+ int8_t rssi[32];
+ /*! \brief Received RSSI values */
+ int rssi_count;
+ /*! \brief Number of stored value */
+ int rssi_valid_count;
+ /*! \brief Any burst received so far */
+ int rssi_got_burst;
+ /*! \brief Sum of TOA values */
+ float toa_sum;
+ /*! \brief Number of TOA value */
+ int toa_num;
+ } meas;
+};
+
+struct trx_ts {
+ /*! \brief Timeslot index within a frame (0..7) */
+ uint8_t index;
+ /*! \brief Last received frame number */
+ uint32_t mf_last_fn;
+
+ /*! \brief Pointer to multiframe layout */
+ const struct trx_multiframe *mf_layout;
+ /*! \brief Channel states for logical channels */
+ struct trx_lchan_state *lchans;
+ /*! \brief Queue primitives for TX */
+ struct llist_head tx_prims;
+ /*! \brief Link to parent list */
+ struct llist_head list;
+};
+
+extern const struct trx_lchan_desc trx_lchan_desc[_TRX_CHAN_MAX];
+const struct trx_multiframe *sched_mframe_layout(
+ enum gsm_phys_chan_config config, int ts_num);