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authorSylvain Munaut <tnt@246tNt.com>2013-01-16 22:55:24 +0100
committerSylvain Munaut <tnt@246tNt.com>2014-06-15 19:30:52 +0200
commit7e9ff0bb561d6e0ae0eb413e87b09f9c29f2f86c (patch)
tree0240e3975f2cf37f946122edfc1515ce4a5d8d9e
parent8fe72b6ebd9718da9acb79ea2e0cc0341fead289 (diff)
fw/calypso/uart: Tweak the RX irq threshold to avoid overrun
We use the extended mode to have a better control Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
-rw-r--r--src/target/firmware/calypso/uart.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/target/firmware/calypso/uart.c b/src/target/firmware/calypso/uart.c
index ec587de5..d843b071 100644
--- a/src/target/firmware/calypso/uart.c
+++ b/src/target/firmware/calypso/uart.c
@@ -313,7 +313,6 @@ void uart_init(uint8_t uart, uint8_t interrupts)
uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */
uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */
uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */
- uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */
/* select UART mode */
uart_reg_write(uart, MDR1, 0);
@@ -323,6 +322,9 @@ void uart_init(uint8_t uart, uint8_t interrupts)
uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
(3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT));
+ /* Override RX irq threshold */
+ uart_reg_write(uart, TLR, (8 << 4) | (0 << 0));
+
/* THR interrupt only when TX FIFO and TX shift register are empty */
uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));