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| author | Vadim Yanitskiy <vyanitskiy@sysmocom.de> | 2020-07-10 20:42:03 +0700 |
|---|---|---|
| committer | Vadim Yanitskiy <vyanitskiy@sysmocom.de> | 2020-07-14 17:21:10 +0700 |
| commit | f262caca7980b27f575d008cb67711de8559db6c (patch) | |
| tree | 9e6c77aeae0b98420a999f0b906b311506f8c8cd | |
| parent | 8d19fbef57f2fa74a63477f7f324f3dc8d5d36d4 (diff) | |
trx_toolkit/clck_gen.py: support optional clock handler
Change-Id: I85b2182d9835ed035cf370e45ea039ac6a7e8405
| -rwxr-xr-x | src/target/trx_toolkit/clck_gen.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/target/trx_toolkit/clck_gen.py b/src/target/trx_toolkit/clck_gen.py index 9f396438..6c09316c 100755 --- a/src/target/trx_toolkit/clck_gen.py +++ b/src/target/trx_toolkit/clck_gen.py @@ -54,6 +54,9 @@ class CLCKGen: self.ctr_interval = self.GSM_FRAME_US - self.LO_DELAY_US self.ctr_interval /= self.SEC_DELAY_US + # (Optional) clock consumer + self.clck_handler = None + @property def running(self): if self._thread is None: @@ -103,6 +106,9 @@ class CLCKGen: # Debug print log.debug(payload.rstrip("\0")) + if self.clck_handler is not None: + self.clck_handler(self.clck_src) + # Increase frame count (modular arithmetic) self.clck_src = (self.clck_src + 1) % GSM_HYPERFRAME |