diff options
author | Harald Welte <laforge@osmocom.org> | 2020-10-11 20:45:23 +0200 |
---|---|---|
committer | laforge <laforge@osmocom.org> | 2020-10-12 13:12:26 +0000 |
commit | e37f9a504fd0ab635edcb2d4d6932e89ce867302 (patch) | |
tree | b09ca209f7a14de8a7a1589688e621dd5d6f8979 | |
parent | 762202288b3ad525b2b5b227851d21a8b688f420 (diff) |
bts: Fix TC_rach_load_idle_thresh0()
The first RACH LOAD IND may only cover a fractional reporting
interval, and hence must be ignored.
Change-Id: I43ee8e846803e2ef6218a3e7ac385ed8af30c217
-rw-r--r-- | bts/BTS_Tests.ttcn | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bts/BTS_Tests.ttcn b/bts/BTS_Tests.ttcn index 57de013d..7c17e035 100644 --- a/bts/BTS_Tests.ttcn +++ b/bts/BTS_Tests.ttcn @@ -1470,6 +1470,12 @@ testcase TC_rach_load_idle_thresh0() runs on test_CT { f_init(); + /* Skip the first RACH LOAD IND, as it may not have the full slot count (BTS started less than 1s before) */ + alt { + [] RSL_CCHAN.receive(tr_ASP_RSL_UD(tr_RSL_RACH_LOAD_IND(?, ?, ?))) { } + [] RSL_CCHAN.receive { repeat } + } + timer T := 5.0; T.start; alt { |