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2018-05-29e1_xcvr.brd: minor routing improvement on TRING signalHEADmasterMartin Schramm1-21/+26
2018-05-29replace old PULSE_T1094NL footprint, repair pin assignment (solves OSM#3269)Martin Schramm2-225/+243
2018-05-29laforge.lbr: PULSE_T1094NL: better tPlace and tDocu layer (for OSM#3270)Martin Schramm1-8/+15
2018-05-29connect LIU's pin 44 to GND (solves OSM#3247)Martin Schramm2-48/+61
2018-05-18laforge.lbr: repair PULSE_T1094NL footprint and symbol (solves OSM#3270)Martin Schramm1-57/+57
... and OSM#3271. - The transformer symbol is made of two identical coils and hence it is not possible to mark the "2:" side (pins 9-11) separately. But the naming of this coil was changed in a way, that, when invoked, the "2" of the subpart name "TR1-1:2" shows towards the pins 9-11. Maybe we should evolve to a device symbol with two coils merged rather than two identical but separated, then an individual naming could honour the 2:1 side and can not be disturbed by e.g. subsequent mirroring. - Also repaired the name and value designators' layer association.
2018-05-16sam4s-e1.gnumeric: Avoid EXT4, add wire colorsHarald Welte1-26/+30
2018-05-16src: Add .gitignore for the softwareSylvain Munaut1-0/+3
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-05-16osmo_e1f: Fix Makefile to use pkg-configSylvain Munaut1-2/+2
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-05-16Merge branch 'laforge/software'Harald Welte7-0/+1223
2018-05-16rename osmo_e1 to osmo_e1f ("f" for "framer")Harald Welte5-106/+106
2018-05-12osmo_e1: fix make cleanHarald Welte1-1/+1
2018-05-12CRC4: use proper CRC4 table to avoid bit-reversal of each byteHarald Welte3-35/+165
In commit 9bd2c9ffe7cf82c5d0a12406db018717d9b78858 we fixed the CRC4 computation by bit-reversing every byte before using it in the CRC table. This is of course a waste of CPU cycles. Let's just compute the CRC4 table slightly different (thanks to Dietter): The following commands using pycrc from pycrc.org were used: ./pycrc.py --width=4 --poly=0x3 --reflect-in=false --reflect-out=false --xor-out=0 --xor-in=0 --algorithm table-driven --generate c -o crc4itu.c ./pycrc.py --width=4 --poly=0x3 --reflect-in=false --reflect-out=false --xor-out=0 --xor-in=0 --algorithm table-driven --generate h -o crc4itu.h
2018-05-11add e1_test_dieter to deframe/decode dieters captureHarald Welte2-1/+87
2018-05-11osmo_e1: Add HDLC framing/deframingHarald Welte3-10/+61
2018-05-11osmo_e1: Silence the FSM loggingHarald Welte1-1/+1
2018-05-11HACK to make CRC4 computation workHarald Welte2-5/+6
* reverse bit-order of every input byte when computing CRC4 * reverse bit-order of CRC4 value we receive in TS0 bits I don't really understand why, but this makes the CRC check pass. We probably need another table if we want to avoid this.
2018-05-11osmo_e1.c: Fix handling of TS2..31 (use 'i', not '1')Harald Welte1-1/+1
2018-05-07add some information related a SAM4S based USB-to-LIU adapter board ideaHarald Welte4-0/+1440
2018-05-07WIP: Software for E1 mux/demuxHarald Welte6-0/+955
2012-07-21add E1 tap hardware designHarald Welte14-0/+8925
2012-07-01laforge.lbr: fix amphenol sim reader footprintHarald Welte1-9/+12
2012-07-01major update of laforge.lbr with lots of new componentsHarald Welte1-114/+2715
2012-03-06add some glue code between the idt82 driver and at91lib SPIHarald Welte3-0/+63
2012-03-06'new' PCB routing by Christian VogelHarald Welte1-0/+0
2012-02-20major update of laforge.lbr with lots of new componentsHarald Welte1-24/+1379
2012-01-14add initial driver skeleton for idt82v2081 chipHarald Welte3-0/+213
2012-01-14give parts names without "$", use 47nH as L1 (1206)Harald Welte2-284/+149
2011-12-26approve lots of warnings about thinner wiresHarald Welte1-1/+137
Christan has routed lots of wires thinner than what the network specific rules state. We approve all of them as we don't care about thinner wires.
2011-12-26remove stray GNDIO wire, add junction, approve some warningsHarald Welte1-5/+4
2011-12-26re-route complete board, add PWR jumper, LED series resistorChristian Vogel2-811/+684
2011-12-24add partlist/bomHarald Welte1-0/+56
2011-12-24update schematics and PCB layoutHarald Welte2-0/+0
2011-12-24re-route pcb with LEDsHarald Welte1-280/+391
2011-12-24add two LEDs (power and LOS) plus required transistorHarald Welte1-11/+3039
2011-12-24re-route the entire board to add test pads and additional componentsHarald Welte1-474/+599
2011-12-24just name some signals/networksHarald Welte1-7/+7
2011-12-24add solder jumper to bypass TPS736XX (if it is not populated)Harald Welte1-0/+101
2011-12-24add 4 test pads for RTIP/RRING/TTIP/TRINGHarald Welte1-4/+716
2011-12-24re-wire SPI connector to reflect pin-out of Olimex devel board UEXTHarald Welte1-77/+78
2011-12-24Add LDO, remove jumpers, 3nd RJ45, ...Harald Welte4-933/+1101
2011-12-24add README fileHarald Welte1-0/+89
2011-12-23initial checkinHarald Welte13-0/+11729