diff options
| author | Harald Welte <laforge@gnumonks.org> | 2012-04-26 20:13:49 +0200 |
|---|---|---|
| committer | Harald Welte <laforge@gnumonks.org> | 2012-04-26 20:13:49 +0200 |
| commit | c1a989f886183949f2dab8a19ab9e11783e74566 (patch) | |
| tree | 645bee24593cec41196c2540e618c36e086cf2b8 | |
| parent | a45232b810868a49ba343a46740cf2125c338966 (diff) | |
enable SPI clock
| -rw-r--r-- | src/cc32/cc32_irq.c | 11 | ||||
| -rw-r--r-- | src/cc32/cc32_spi.c | 5 | ||||
| -rw-r--r-- | src/cc32/cc32_sysc.h | 27 |
3 files changed, 42 insertions, 1 deletions
diff --git a/src/cc32/cc32_irq.c b/src/cc32/cc32_irq.c index a382409..d9cb62c 100644 --- a/src/cc32/cc32_irq.c +++ b/src/cc32/cc32_irq.c @@ -1,4 +1,5 @@ +#include "cc32_sysc.h" #include "cc32_irq.h" #define CC32_SYSC_BASE 0x0F0000 @@ -38,3 +39,13 @@ void cc32_irq_register(enum cc32_irq irq, void (*handler)(enum cc32_irq irq)) { /* FIXME */ } + +void cc32_sysc_clk_enable(enum cc32_clk clk) +{ + *SYSC_REG(SCCM0) |= clk; +} + +void cc32_sysc_clk_disable(enum cc32_clk clk) +{ + *SYSC_REG(SCCM0) &= ~clk; +} diff --git a/src/cc32/cc32_spi.c b/src/cc32/cc32_spi.c index 09ea845..03aca17 100644 --- a/src/cc32/cc32_spi.c +++ b/src/cc32/cc32_spi.c @@ -19,11 +19,12 @@ #include <errno.h> +#include "cc32_sysc.h" #include "cc32_spi.h" #define CC32_SPI_BASE 0x0f9800 -enum cc32_flcon_reg { +enum cc32_spi_reg { SPICON2 = 0x08, SPIDAT = 0x0C, SPISTS = 0x10, @@ -61,6 +62,8 @@ int cc32_spi_init(uint8_t cpol, uint8_t cpha, uint8_t divide_2n) { uint32_t val; + cc32_sysc_clk_enable(CLK_SPI); + if (divide_2n < 2 || divide_2n > 256) return -EINVAL; diff --git a/src/cc32/cc32_sysc.h b/src/cc32/cc32_sysc.h new file mode 100644 index 0000000..69f82a9 --- /dev/null +++ b/src/cc32/cc32_sysc.h @@ -0,0 +1,27 @@ +#ifndef _CC32_SYSC_H +#define _CC32_SYSC_H + +#include <stdint.h> + +enum cc32_clk { + CLK_TIMER = (1 << 0), + CLK_CRC = (1 << 2), + CLK_DES = (1 << 3), + CLK_AES = (1 << 4), + CLK_RSA = (1 << 5), + CLK_FLASH = (1 << 8), + CLK_RAM0 = (1 << 11), + CLK_RAM12 = (1 << 12), + CLK_ISO7816 = (1 << 16), + CLK_GPIO = (1 << 18), + CLK_SPI = (1 << 20), + CLK_VD = (1 << 24), + CLK_FD = (1 << 25), + CLK_RNG = (1 << 27), + CLK_DMA = (1 << 28), +}; + +void cc32_sysc_clk_enable(enum cc32_clk clk); +void cc32_sysc_clk_disable(enum cc32_clk clk); + +#endif |