add VTY based way to set clock calibration of sysmobts L1

4 files changed, 50 insertions, 2 deletions

diff --git a/src/osmo-bts-sysmo/l1_if.c b/src/osmo-bts-sysmo/l1_if.c
index 59db61fd..39e356f8 100644
--- a/src/osmo-bts-sysmo/l1_if.c
+++ b/src/osmo-bts-sysmo/l1_if.c
@@ -720,7 +720,7 @@ int l1if_activate_rf(struct femtol1_hdl *hdl, int on)
 
 	if (on) {
 		sysp->id = FemtoBts_PrimId_ActivateRfReq;
-		sysp->u.activateRfReq.u12ClkVc = 0xFFFF;
+		sysp->u.activateRfReq.u12ClkVc = hdl->clk_cal;
 	} else {
 		sysp->id = FemtoBts_PrimId_DeactivateRfReq;
 	}
@@ -847,6 +847,7 @@ struct femtol1_hdl *l1if_open(void *priv)
 	INIT_LLIST_HEAD(&fl1h->wlc_list);
 
 	fl1h->priv = priv;
+	fl1h->clk_cal = 0xffff;
 
 	rc = l1if_transport_open(fl1h);
 	if (rc < 0) {
diff --git a/src/osmo-bts-sysmo/l1_if.h b/src/osmo-bts-sysmo/l1_if.h
index 09f84ef0..1b150d38 100644
--- a/src/osmo-bts-sysmo/l1_if.h
+++ b/src/osmo-bts-sysmo/l1_if.h
@@ -21,6 +21,7 @@ struct femtol1_hdl {
 	struct gsm_time gsm_time;
 	uint32_t hLayer1;			/* handle to the L1 instance in the DSP */
 	uint32_t dsp_trace_f;
+	uint16_t clk_cal;
 	struct llist_head wlc_list;
 
 	void *priv;			/* user reference */
diff --git a/src/osmo-bts-sysmo/main.c b/src/osmo-bts-sysmo/main.c
index 645cd24a..0ed6e2c8 100644
--- a/src/osmo-bts-sysmo/main.c
+++ b/src/osmo-bts-sysmo/main.c
@@ -51,7 +51,7 @@ const char *software_version = "0815";
 static const char *config_file = "osmo-bts.cfg";
 extern const char *osmobts_copyright;
 static int daemonize = 0;
-static unsigned int dsp_trace = 0;
+static unsigned int dsp_trace = 0xffffffff;
 
 int bts_model_init(struct gsm_bts *bts)
 {
diff --git a/src/osmo-bts-sysmo/sysmobts_vty.c b/src/osmo-bts-sysmo/sysmobts_vty.c
index 78ad6c93..93dd024b 100644
--- a/src/osmo-bts-sysmo/sysmobts_vty.c
+++ b/src/osmo-bts-sysmo/sysmobts_vty.c
@@ -39,6 +39,7 @@
 
 #include <osmo-bts/gsm_data.h>
 #include <osmo-bts/logging.h>
+#include <osmo-bts/vty.h>
 
 #include "femtobts.h"
 #include "l1_if.h"
@@ -99,6 +100,35 @@ err:
 	return str;
 }
 
+/* configuration */
+
+DEFUN(cfg_trx_clkcal_def, cfg_trx_clkcal_def_cmd,
+	"clock-calibration default",
+	"Set the clock calibration value\n" "Default Clock DAC value\n")
+{
+	unsigned int clkcal = atoi(argv[0]);
+	struct gsm_bts_trx *trx = vty->index;
+	struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
+
+	fl1h->clk_cal = 0xffff;
+
+	return CMD_SUCCESS;
+}
+
+DEFUN(cfg_trx_clkcal, cfg_trx_clkcal_cmd,
+	"clock-calibration <0-4095>",
+	"Set the clock calibration value\n" "Clock DAC value\n")
+{
+	unsigned int clkcal = atoi(argv[0]);
+	struct gsm_bts_trx *trx = vty->index;
+	struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
+
+	fl1h->clk_cal = atoi(argv[0]) & 0xfff;
+
+	return CMD_SUCCESS;
+}
+
+/* runtime */
 
 DEFUN(show_dsp_trace_f, show_dsp_trace_f_cmd,
 	"show trx <0-0> dsp-trace-flags",
@@ -210,6 +240,19 @@ DEFUN(show_sys_info, show_sys_info_cmd,
 	return CMD_SUCCESS;
 }
 
+void bts_model_config_write_bts(struct vty *vty, struct gsm_bts *bts)
+{
+}
+
+void bts_model_config_write_trx(struct vty *vty, struct gsm_bts_trx *trx)
+{
+	struct femtol1_hdl *fl1h = trx_femtol1_hdl(trx);
+
+	if (fl1h->clk_cal != 0xffff) {
+		vty_out(vty, "  clock-calibration %u%s", fl1h->clk_cal,
+			VTY_NEWLINE);
+	}
+}
 
 int bts_model_vty_init(struct gsm_bts *bts)
 {
@@ -226,5 +269,8 @@ int bts_model_vty_init(struct gsm_bts *bts)
 	install_element_ve(&dsp_trace_f_cmd);
 	install_element_ve(&no_dsp_trace_f_cmd);
 
+	install_element(TRX_NODE, &cfg_trx_clkcal_cmd);
+	install_element(TRX_NODE, &cfg_trx_clkcal_def_cmd);
+
 	return 0;
 }